基于FPGA循环冗余校验码系统设计

摘要

Generating error problem during transmission systems for digital communication signal is pro-posed based on FPGA cyclic redundancy check code system.The use of hardware description language VHDL design implementation and verification process of generating cyclic redundancy check code gener-ated by the verification and simulation software for the hardware platform QuartusII CRC,complete the de-sign of the entire calibration system through test:The system improves communication quality,shorten the design cycle and reduce the error rate in the communication to ensure the correctness and completeness of the data,and improve the reliability of data communication,there is a certain value in engineering.%针对数字通信系统信号在传输过程中产生误码问题，该文提出了基于FPGA循环冗余校验码的系统。利用硬件描述语言VHDL设计实现了循环冗余校验码的生成和校验过程，通过硬件平台QuartusII软件对CRC生成与校验的仿真验证，完成整个校验系统的设计，通过测试：系统提高了通信质量，缩短了设计周期，降低了通信中的误码率保证了数据的正确性和完整性，提高了数据通信的可靠性，有一定的工程应用价值。