DCF77时间码解码方案的设计

摘要

A decoding scheme based on FPGA is proposed with emphasis on analyzing and processing code element re-cognition.A FSM is designed for recognition of different code-elements and data recording.Modelsim functional simulation validates the accuracy and availability of the scheme.Compared with the IRIG-B code, the proposed scheme adds the week information at a frame length of only 60 bit, which is the same with time radix.This scheme has the advantage of simplicity, stability and easy implementation.%提出了一种基于FPGA的DCF77解码方案设计.实现过程中着重针对码元识别部分进行分析,设计了一种有限状态机来完成对不同码元的识别以及数据写入等.通过Modelsim软件对程序进行了功能仿真,验证了该方案可以正确的进行时间解码.相比常用的IRIG-B码,增加了星期的信息,并且每一帧只有60位,恰好与时间进制相同,具有代码简单、工作稳定性强、易于移植等优点.