基于IEEE Std1500的IP核并行测试控制架构设计

摘要

随着IEEE 1500标准的不断推广应用,兼容该标准的IP核也越来越多,具有IEEE 1500标准结构的IP核也被越来越多的应用到片上系统的设计中；由于IEEE 1500标准定义了外壳架构和测试访问机制,因此如何实现片上系统中IP核的外壳架构和测试访问机制的测试控制便成为研究的热点问题；文章在研究标准的基础上,基于外壳架构和CAS-BUS测试访问机制,提出IP核的并行测试控制架构,通过多IP核的仿真时序图分析,验证了测试控制架构的有效性；该架构能够实现多IP核的并行测试控制,节约了测试时间,提高了测试效率,为片上系统的测试控制提供一种新思路.%With the development of IEEE Stdl500, IP cores which are compatible with this standard are more and more, and test control research aimed at the kind of IP cores becomes a view of interest. Based on wrapper architecture and CAS-BUS test access mechanism, a parallel test control architecture is proposed. Through analysis of instruction simulation, architecture's validity is proved. This architecture can realize parallel test of IP cores, save test time and improve test efficiency.