一种同步输出的稀疏树前导零检测电路

摘要

为了降低前导零检测电路的延时和提高端口输出的同步性,提出了一种稀疏树前导零检测结构及动态电路的实现方法.通过递归前导零算法表达式定义了两种新的布尔运算逻辑,以构成稀疏树中的结点.精确控制动态电路中预充时钟的偏移量,在抑制电路漏电的同时控制输出端口延时差.该结构能够以最少的逻辑级数和均衡的运算单元负载实现检测前导零功能,对于不同数量的待测信号,通过扩展"点操作"和"块操作"单元互连网络来生成新电路.采用伪随机激励向量验证了电路功能的正确性,大幅缩短了验证时间,在SMIC 40nm工艺下仿真显示,各端口输出延时差小于1ps,数据路径长度可降低20%.%To reduce the delay and the arrival time difference of a leading-one-detector circuit, a sparse-tree based leading-one-detector structure and its dynamic circuit implementation method were presented.Two new kinds of logical Boolean operations were defined by recursive expression to form the nodes of the sparse tree.The precalculated clock''s skew in the pre-charge stage can be accurately controlled, so the leakage power and the arrival time difference can be simultaneously controlled.In consideration of the various numbers of input ports, the extending network by connecting same spot units shortens the time cost on designing.There is less logic level and fan-out in the structure presented.The whole circuit was verified by the pseudo random test vector.This technique could reduce the critical path length by 20% and keep the arrival time in 1 picosecond.