基于自适应时序匹配的低延迟寄存器堆

摘要

指出半导体工艺与晶体管特性参数的随机波动随着芯片特征尺寸不断减小越来越大,传统的基于预匹配的寄存器堆设计方法必须通过增大匹配裕量来保证读写操作的可靠性,为了克服制约寄存器堆性能提升的这一关键因素,提出了一种基于自适应时序匹配的低功耗寄存器堆电路结构.该结构通过对多端口寄存器堆的访存时序进行自适应匹配与调优,达到减小寄存器堆访问延时、降低功耗以及提高芯片工艺敏感度的目的.电路及版图仿真结果显示:基于该方法实现的3读2写32×64 bit寄存器堆,在SMIC 40nm工艺条件下,芯片面积为135.5μm×65.1μm,访存延迟为357ps,相比于传统的Chain Delay匹配技术,延迟减小22%,功耗降低35%.%It is pointed that the random variation of the characteristic parameters of semiconductor process and transistors gets bigger with the decrease of the chip feature size,thus the traditional register file design based on prematch has to increase the matching margin to ensure the reliability of read and write operations.To overcome this key factor of restricting register file performance,a low power register file circuit structure based on adjustable access latency is proposed.The proposed mechanism can auto-test the practical path delay of the sense amplifier,and automatically match and tune time delay of sense enable signals to guarantee the correct operation,so as to improve the perform-ance and power of the circuit by reducing unnecessary margin pre-placed in design.For 3-read ports and 2-write ports 32×64bit register file generated in SMIC 40nm technology,its area is 135.5μm×65.1μm and read access latency is 357ps.The simulation results show that compared with the traditional chain delay technique,the read ac-cess latency and the power consumption of the mechanism are reduced by 22%and 35%respectively.