Thin p + layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post FA (furance annealing) of Si +/B + dual implanted silicon wafers. The electrical and structural characteristics of thin p + layers have been measured by FPP (four point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p +n junctions can be fabricated, which shows excellent I V characteristics with revers bias leakage current densities of 1.8?nA/cm 2 at -1.4?V.
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