followed with smartphone platform and PAD rising performance requirement in the market backend design engineers meet the great design pressure. Traditional digital implementation flow is reaching the ceiling in terms of frequency ,power and area requirements for today＇s SoC designs. How quickly within a very short time to achieve chip performance ,good power consumption and less area are particularly important. This article is based on SMIC 40nm low-power process ARM Cortex A9 physical design and describe in detail how to use the cadence latest clock concurrent optimization technique to achieve a unified clock tree synthesis and physical optimization methodology. According to the testing results CCopt get the good performance and have achieved 8% frequency increase, power reduction and area decrease .Cadence CCopt technique brings a lot of advantages in the implementation of complex chip physical design,shorten design cycle time and performance improvement.%随着市场智能手机平台和平板电脑对芯片性能和上市时间要求的不断提升，后端工程师面临的设计压力会越来越大。传统的数字实现流程在满足当今SoC设计的功耗、频率与面积要求方面正在达到极限。那如何在很短的时间内迅速实现芯片功耗、频率与面积的提升变的尤为重要。本文基于SMIC40nm低功耗工艺的ARM CorrexA9物理设计的实际情况，详细阐述了如何使用cadence最新的时钟同步优化技术，又称为CCopt技术来实现统一的时钟树综合和物理优化。根据实现的结果来看，CCopt引擎很好的实现了目标。实现8％的设计频率提升，并实现了时钟树功率与面积降低。Cadence最新的CCopt引擎对实现复杂芯片物理设计、缩短设计周期、提升芯片性能带来了很大的优势。
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