In order to meet the market demand of improving the reading and writing efficiency of reader, a kind of RFID reader design plan based on ISO 18000-6C protocol is presented. Digital baseband circuit includes ARM and FPGA. Due to the advantage of FPGA in fast encoding and decoding, and the advantage of ARM in controlling, the reader has characterristic of high recognition and recognize effectively. In circuit design of RF circuit, two amplifiers are used in order to reduce noise effectively, gain well linearity, win high radiant power and recognize tags at a distance. The receiving circuit includes four ways of demodulation, so that the "fuzzy point" can be solved.%为了满足市场需求,提高阅读器读写效率,提出一种基于IS018000-6C协议标准的RFID阅读器设计方案.该阅读器基带处理部分采用ARM+ FPGA组合实现,利用FPGA编解码速度快的特点并结合ARM的控制优势,使得该阅读器具有识别速度快、识别率高的特点;阅读器的射频发射电路采用两级功率放大,具备能很好地抑制噪声、保持很好的线性度、辐射功率满足要求、识别距离远的特点;阅读器的接收回路采用四路解调,可以很好地解决接收“模糊点”.
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