标准芯片单元可连通性的检测方法

摘要

This paper presents a method for detecting the connectivity of standard chip units.This method can effectively detect the connectivity of the standard chip unit,improve the layout of the standard cell before the place and routing,or enhance the constraints of the place and routing,so as to ensure the design of the standard chip unit is friendly to place and routing.Through the detection and improvement of the standard chip unit,it can effectively improve the overall connectivity of the chip,then the turnaround time of place and route stage can be saved,the development cycle can be reduced and the chip yield can be improved.This method can realize the full coverage detection of the standard chip cell library.Through the algorithm optimization,more than 90％ of the random scenario can be realized under the premise of minimizing the workload of the chip test.This method effectively captures the connectivity of standard chip units through the application of standard chip unit detection in different technology nodes.It improves or discards unfriendly scenarios that may occur before the digital back-end place and routing,and improves the efficiency of the chip back-end design.%介绍了一种标准芯片单元可连通性的检测方法,可以有效检测标准芯片单元的可连通性,在布局布线阶段之前,改进标准单元的版图,或者增加布局布线的约束条件,从而保证标准芯片单元的设计对布局布线的友好性.通过对标准芯片单元的检测和改进,可以有效提高芯片的整体可连通性,从而节约布局布线阶段的工作时间,减少开发周期,提高芯片良率.本方法可以实现标准芯片单元库的全覆盖检测,通过优化算法,可以在尽可能减少芯片测试工作量的前提下,实现90％以上的随机场景再现.通过在不同技术节点标准芯片单元检测中的应用,有效地捕获了标准芯片单元连通性的问题,在数字后端布局布线之前,改进或阻止了可能出现的不友好场景,提升了芯片后端设计的效率.