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Interfaces and junctions in bottom-up nanoscale semiconductor devices.

机译:自底向上的纳米级半导体器件中的界面和结。

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摘要

A semiconductor device is a system composed of multiple materials, and its functionality depends on the junctions and interfaces between these materials. This dissertation documents a study of junctions and interfaces in one-dimensional nanoscale semiconductor materials. Examined are the insulator interface and the dopant profile in vapor-liquid-solid (VLS)-grown silicon nanowires, the electronic properties of the native surface of InAs nanowires grown using bottom-up methods, and metal-carbon nanotube (CNT) Schottky contacts. The capacitance-voltage (C-V) measurement is refined to examine these junctions and interfaces. For a Si nanowire, the C-V measurement shows that the density of trap states on its interface with Al2O3 insulator ranges from ∼1011/cm2·eV in the midgap to ∼1013/cm2·eV closer to the valence band edge. The boron profile in Si nanowires is found to agree well with predictions from interstitial and vacancy-assisted diffusion model, as in bulk Si. For an InAs nanowire, the C-V technique is used extract the trap density of its native surface, which is ∼3.8x1011/cm2·eV in the mid-gap and ∼1013/cm2·eV near the conduction band edge. The trap lifetime in these InAs nanowires is extracted using the C-V method as well. Accurate measurement of the gate capacitance in back-gated InAs nanowires is found to be necessary to determine accurately the electron mobility. The impact of metal-CNT Schottky contacts on the transistor performance and leakage is examined as well. It is found that both the on-state current and off-state leakage depend strongly on the Schottky Barrier Height (SBH) at the contacts. The scaling of the SBH with the CNT diameter shows that the length of the electrical junction is about 25nm. The metal-CNT Schottky junction is also studied using a new instrument capable of measuring rapidly attofarad (10-18 F)-level capacitances. This study confirms the unpinned nature of the metal-CNT Schottky contact, and shows a way to directly determine the height of that energy barrier.
机译:半导体器件是由多种材料组成的系统,其功能取决于这些材料之间的结和界面。本文对一维纳米尺度半导体材料的结和界面进行了研究。检查了在气液固(VLS)生长的硅纳米线中的绝缘体界面和掺杂剂分布,使用自下而上方法生长的InAs纳米线的自然表面的电子特性以及金属碳纳米管(CNT)肖特基接触。改进了电容电压(C-V)测量以检查这些结和界面。对于Si纳米线,C-V测量表明,其与Al2O3绝缘体的界面处的陷阱态密度在中能隙的〜1011 / cm2·eV到更接近价带边缘的〜1013 / cm2·eV。发现Si纳米线中的硼分布与填隙Si和空位辅助扩散模型的预测非常吻合,就像块状Si一样。对于InAs纳米线,使用C-V技术提取其自然表面的陷阱密度,在中间间隙约为3.8x1011 / cm2·eV,在导带边缘附近约为1013 / cm2·eV。这些InAs纳米线中的陷阱寿命也使用C-V方法提取。已经发现,对背栅InAs纳米线中栅极电容的准确测量对于准确确定电子迁移率是必要的。还检查了金属CNT肖特基接触对晶体管性能和泄漏的影响。发现导通状态电流和关断状态泄漏都强烈取决于触点处的肖特基势垒高度(SBH)。 SBH与CNT直径的比例关系表明,电结的长度约为25nm。还使用一种能够快速测量法拉第(10-18 F)级电容的新型仪器研究了金属-CNT肖特基结。这项研究证实了金属-CNT肖特基接触的非固定性质,并显示了直接确定该势垒高度的方法。

著录项

  • 作者

    Tseng, Yu-Chih.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Electronics and Electrical.;Engineering Materials Science.;Physics Condensed Matter.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 108 p.
  • 总页数 108
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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