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Nanowire Specialty Diodes for Integrated Applications.

机译:适用于集成应用的纳米线特种二极管。

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摘要

Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation.;In this study, vertical Ge and Si nanowire Schottky diodes have been fabricated using bottom-up vapor-liquid-solid (VLS) and top-down reactive ion etching (RIE) approaches respectively. VLS growth yields nanowires with atomically smooth sidewalls at sub-50 nm diameters but suffers from the problem that the doping increases radially outwards from the core of the devices. RIE is much faster than VLS and does not suffer from the problem of non-uniform doping. However, it yields nanowires with rougher sidewalls and gets exceedingly inefficient in yielding vertical nanowires for diameters below 50 nm. The I-V characteristics of both Ge and Si nanowire diodes cannot be adequately fit by the thermionic emission model. Annealing in forming gas which passivates dangling bonds on the nanowire surface is shown to have a considerable impact on the current through the Si nanowire diodes indicating that fixed charges and traps on the surface of the devices play a major role in determining their electrical behavior. Also, due to the vertical geometry of the nanowire diodes, electric field lines originating from the metal and terminating on their sidewalls can directly modulate their conductivity. Both these effects have to be included in the model aimed at predicting the current through vertical nanowire diodes.;This study shows that the current through vertical nanowire diodes cannot be predicted accurately using the thermionic emission model which is suitable for planar devices and identifies the factors needed to build a comprehensive analytical model for predicting the current through vertically oriented nanowire diodes.
机译:半导体纳米线是高度缩放的三维电子设备的重要候选者。通过将纳米线器件集成到平面电路中,将其缩放功能与平面CMOS技术的高产量相结合是非常有利的。这项研究的目的是确定与垂直取向的Si和Ge纳米线二极管制造相关的挑战并对其电性能进行建模,以便可以利用它们创建独特的三维体系结构,从而可以将电子设备的规模扩展到下一个在这项研究中,垂直的Ge和Si纳米线肖特基二极管分别使用自下而上的气液固(VLS)和自上而下的反应离子刻蚀(RIE)方法制造。 VLS的生长产生纳米线,其原子直径小于50nm的原子侧壁光滑,但是存在这样的问题,即掺杂从器件的核心径向向外增加。 RIE比VLS快得多,并且不存在掺杂不均匀的问题。然而,它产生具有更粗糙侧壁的纳米线,并且在产生直径小于50nm的垂直纳米线方面变得极其无效。热电子发射模型无法充分拟合Ge和Si纳米线二极管的I-V特性。钝化纳米线表面上的悬空键的形成气体中的退火显示出对通过Si纳米线二极管的电流有相当大的影响,表明器件表面上的固定电荷和陷阱在确定其电学行为中起主要作用。同样,由于纳米线二极管的垂直几何形状,源自金属并终止于其侧壁的电场线可以直接调节其导电性。这两种效应都必须包含在旨在预测通过垂直纳米线二极管的电流的模型中;这项研究表明,使用适合平面器件的热电子发射模型无法准确预测通过垂直纳米线二极管的电流,并确定了因素需要建立一个全面的分析模型来预测通过垂直取向的纳米线二极管的电流。

著录项

  • 作者

    Chandra, Nishant.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 164 p.
  • 总页数 164
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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