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Machine Learning-inspired High-performance and Energy-efficient Heterogeneous Manycore Chip Design

机译:机器学习启发的高性能和节能异构Manycore芯片设计

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摘要

CPU-GPU based heterogeneous manycore architecture is expected to be the dominant computing platform for many emerging application domains including artificial intelligence, bio-computing and big data analytics. This heterogeneous system typically consists of multiple CPU cores, many GPU cores and a few shared Last-Level-Cache (LLC) units and exhibit challenging on-chip traffic patterns with various QoS requirements. The on-chip communication architecture for heterogeneous manycore systems should be designed such that it efficiently handles the various traffic requirement simultaneously. With the incorporation of different types (CPUs, GPUs, accelerators, etc.) of cores, it becomes more difficult to efficiently explore the combinatorial design space of heterogeneous systems. In order to uncover high-quality designs, new methods need to be developed that can quickly search the design space with ever increasing system size.;Aside from on-chip communication architecture, the design of heterogeneous manycore platforms is dominated by power and thermal constraints. In this respect, voltage--frequency island (VFI) is a promising design paradigm to create scalable energy-efficient platforms. By dynamically tailoring the voltage and frequency of each island, we can further improve the energy savings within given performance constraints. Traditional DVFS techniques operate on a core-by-core basis and use core-level information (e.g., core utilization and communication) to tailor the V/F values of each individual core. These traditional DVFS techniques were applied using the combined information from all cores within the VFI, i.e., the VFI's average core utilization and communication. However, simple averages may not capture the information required to accommodate every core, router, and link within a VFI, particularly for VFIs with large intra-VFI workload variance.;In this dissertation, we undertake above-mentioned problems of designing efficient heterogenous manycore architectures. First, we propose a hybrid Network-on-Chip architecture consisting of both wireline and wireless links that can seamlessly handle the varied traffic requirements that arise in heterogeneous manycore platforms. Second, we develop a machine learning-based multi-objective optimization (MOO) algorithm that learns an evaluation function and guides the search toward optimal designs in heterogeneous manycore systems. Finally, we propose architecture-independent imitation learning-based methodology for dynamic VFI control in heterogeneous manycore systems to address power and thermal issues.
机译:基于CPU-GPU的异构Manycore架构有望成为许多新兴应用领域(包括人工智能,生物计算和大数据分析)的主要计算平台。这种异构系统通常由多个CPU内核,多个GPU内核和几个共享的最后一级缓存(LLC)单元组成,并展现出具有挑战性的,具有各种QoS要求的片上流量模式。异构多核系统的片上通信体系结构应设计为能够有效地同时处理各种流量需求。随着不同类型(CPU,GPU,加速器等)内核的合并,有效探索异构系统的组合设计空间变得更加困难。为了发现高质量的设计,需要开发新的方法来快速搜索不断增长的系统空间中的设计空间。除了片上通信体系结构以外,异构多核平台的设计还受到功率和热约束的支配。在这方面,电压-频率岛(VFI)是创建可扩展的节能平台的有前途的设计范例。通过动态调整每个孤岛的电压和频率,我们可以在给定的性能约束下进一步提高节能效果。传统的DVFS技术在逐个核心的基础上运行,并使用核心级信息(例如,核心利用率和通信)来调整每个单独核心的V / F值。这些传统的DVFS技术是通过使用VFI中所有核心的组合信息(即VFI的平均核心利用率和通信)来应用的。但是,简单的平均值可能无法捕获容纳VFI中的每个核心,路由器和链路所需的信息,尤其是对于VFI内部工作负荷差异较大的VFI 。;本文中,我们面临上述设计高效异构多核的问题。建筑。首先,我们提出了一种混合的片上网络架构,该架构由有线和无线链路组成,可以无缝处理异构多核平台中出现的各种流量需求。其次,我们开发了一种基于机器学习的多目标优化(MOO)算法,该算法可学习评估函数,并指导异构多核系统中的优化设计搜索。最后,我们为异构多核系统中的动态VFI控制提出了与体系结构无关的基于模仿学习的方法,以解决功率和散热问题。

著录项

  • 作者

    Choi, Wonje.;

  • 作者单位

    Washington State University.;

  • 授予单位 Washington State University.;
  • 学科 Computer engineering.;Computer science.;Electrical engineering.
  • 学位 Ph.D.
  • 年度 2018
  • 页码 134 p.
  • 总页数 134
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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