Rapid technology scaling has enabled the integration of many computational cores into a single chip. Given this level of core integration, the requirements for a large and scalable main memory system will only grow. Current DRAM-based main memory systems face power and scalability issues due to working at sub-micron scales. As existing memory technologies approach their physical limits in terms of scalability and power consumption, system designers have motivated to explore alternative technologies to meet the increasing demand for higher memory capacity. Phase Change Memory (PCM) has been proposed as one of the most promising technology candidates to replace or complement DRAM. PCM provides non-volatility, fast access latency, low power consumption, high scalability and bit-level access. However, dependability issues are the primary impediments toward adoption of PCM for next generation of memory systems.;In this thesis we investigate new and novel architectural support to design dependable non-volatile memories, while introducing minimal overhead. In the first part of the thesis we introduce mechanisms to improve cell wear-out in PCM technology, in order to prolong memory lifetime. PCM cells can only endure a limited number of writes, and will then wear out, therefore, PCM error correcting schemes are a must for reliable operation. Current error correction schemes for PCMs have limited capabilities in tolerating multiple errors. We first propose an error recovery mechanism to tolerate a large number of hard errors to improve reliability of PCMs. Our mechanism exploits metadata for replacing faulty bits -- error detection and location information is not needed. The location of failed memory cells are identified by a read verification, coupled with an extra write operation. Static and a dynamic partitioning schemes are proposed to alleviate the negative impacts of the extra writes, extending memory lifetime. Furthermore, we introduce a block-level cooperation technique that operates on top of error correction mechanisms to increase metadata utilization. Once an error recovery scheme fails to recover from faults in a data block, the entire physical page associated with that block is disabled and becomes unavailable to the physical address space. To reduce the page waste caused by early block failures, other blocks can be used to support the failed block, working cooperatively to keep it alive and extend the faulty page's lifetime. We show how block cooperation can be realized through metadata sharing, and data layout reorganization besides state-of-the-art error correcting schemes.;In the second part of the thesis, we address thermal disturbance in very dense PCMs. Due to the heat generated during the programming of cells, neighboring cells may be disturbed, experiencing changes in their values. A naive solution is to increase inter-cell space, attempting to isolate cell programming and eliminating write disturbance, but this approach significantly reduces PCM density. We propose two cost-effective solutions to reduce the probability of write disturbance. Our solutions come with few side-effects on other memory system metrics. The first technique is based on data encoding, and tries to reduce the number of vulnerable data patterns when writing data to main memory. The second technique detects vulnerable cells, and overwrites them if their occurrence is below a set threshold. The proposed techniques are general and can avoid much of the performance overhead introduced by write disturbance with incurring negligible overhead on energy consumption and memory lifetime.;Lastly, this thesis addresses security as another aspect of dependability in the memory systems. While nonvolatility is a desirable feature to save energy in NVMs, it creates security vulnerabilities, since data will persistent after system power-off. Data stored in NVMs can be secured using data encryption. However, side effects imposed by memory encryption result in excessive bit writes, which will drastically reduce NVM lifetimes and increase energy consumption. We propose Nacre to bridge the gap between fully-encrypted and unencrypted NVMs. The Nacre exploits standard counter-mode encryption to maintain security. By tracking the different versions of the modified data in each memory writeback, the Nacre attempts to limit the number of bit writes. Selective reencryption is performed based on the history of the modified data in cache lines. We show that our security mechanism can improve memory lifetime significantly, with only marginal increases in energy consumption.
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