首页> 外文会议>2012 IEEE Computer Society Annual Symposium on VLSI >NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories
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NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories

机译:NVMain:用于新兴非易失性存储器的体系结构级主存储器模拟器

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Emerging non-volatile memory (NVM) technologies, such as PCRAM and STT-RAM, have demonstrated great potentials to be the candidates as replacement for DRAM-based main memory design for computer systems. It is important for computer architects to model such emerging memory technologies at the architecture level, to understand the benefits and limitations for better utilizing them to improve the performance/energy/reliability of future computing systems. In this paper, we introduce an architectural-level simulator called NV Main, which can model main memory design with both DRAM and emerging non-volatile memory technologies, and can facilitate designers to perform design space explorations utilizing these emerging memory technologies. We discuss design points of the simulator and provide validation of the model, along with case studies on using the tool for design space explorations.
机译:诸如PCRAM和STT-RAM等新兴的非易失性存储器(NVM)技术已显示出巨大的潜力,可以替代计算机系统中基于DRAM的主存储器设计。对于计算机架构师而言,在架构级别对此类新兴内存技术进行建模非常重要,以了解更好地利用它们来改善未来计算系统的性能/能源/可靠性的好处和局限性。在本文中,我们介绍了一种称为NV Main的体系结构级别的模拟器,该模拟器可以使用DRAM和新兴的非易失性存储器技术对主存储器设计进行建模,并可以帮助设计人员利用这些新兴的存储器技术进行设计空间探索。我们讨论了模拟器的设计要点,并提供了模型验证,以及使用该工具进行设计空间探索的案例研究。

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