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A PARALLEL PIPELINE COMPUTER ARCHITECTURE FOR SPEECH PROCESSING.

机译:语音处理的并行管道计算机体系结构。

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The subject of this dissertation is a modular multicomputer architecture for digital speech (and signal) processing that is eminently suitable for implementation using Very Large Scale Integration (VLSI) techniques.; Processors built using this approach consist of several hardware identical computers (called Array Block Computers or ABC's) interconnected to form a number of functional block pipelines operating in parallel. Each ABC is a microprogrammable computer including a Central Processing Unit, Program Memory, Data Memory and a Communications Unit that handles communications with adjacent ABC's.; Data transfers between ABC's occur simultaneously for all ABC's at fixed predetermined intervals. All data exchanges are controlled totally by hardware and they are transparent to the programmer of the ABC's, greatly simplifying programming. The ABC's operate on whole frames of data performing operations such as windowing, the FFT, etc. The interconnecting topology for the ABC's is identical to the block diagram of the function performed. Performance increases linearly with the number of the ABC's in the system.; In order to demonstrate the feasibility of the proposed architecture, a prototype was built using the AMD 2901 4-bit slice microprocessor. Sufficient performance was obtained for complex real-time speech processing at a cost comparable to commercially available signal processors.; It is estimated that it will be possible to interface a whole ABC with performance superior to the current implementation on a silicon chip using 1 micron NMOS technology. A serial communication scheme is proposed that would allow such ABC's to be packaged in an 8-pin package. The very small required pinout and the fact that all ABC's are hardware identical (differing only in their programs) makes them very easy to mass produce using VLSI techniques. This will lead to very low cost, extremely high instruction execution rate computers, an essential requirement for most speech processing applications and especially speech recognition.
机译:本文的主题是用于数字语音(和信号)处理的模块化多计算机体系结构,非常适合使用超大规模集成(VLSI)技术来实现。使用这种方法构建的处理器由若干硬件相同的计算机(称为阵列块计算机或ABC)组成,这些计算机相互连接以形成许多并行运行的功能块管线。每个ABC是一个微可编程计算机,包括中央处理单元,程序存储器,数据存储器和处理与相邻ABC的通信的通信单元。 ABC之间的数据传输以固定的预定间隔同时发生于所有ABC。所有数据交换完全由硬件控制,并且对ABC的程序员是透明的,从而大大简化了编程。 ABC对数据的整个帧进行操作,以执行诸如加窗,FFT等操作。ABC的互连拓扑与所执行功能的框图相同。性能随系统中ABC的数量线性增加。为了证明所提出的体系结构的可行性,使用AMD 2901 4位Slice微处理器构建了原型。复杂的实时语音处理获得了足够的性能,其成本可与市售信号处理器相媲美。据估计,使用1微米NMOS技术可以使整个ABC接口具有优于当前在硅芯片上实现的性能。提出了一种串行通信方案,该方案允许将此类ABC封装在8引脚封装中。所需的引脚排列非常小,而且所有ABC的硬件都是相同的(仅在其程序上有所不同),这使得使用VLSI技术非常容易批量生产它们。这将导致成本非常低,指令执行速度极高的计算机,这是大多数语音处理应用(尤其是语音识别)的基本要求。

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