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Compatibility studies of zinc oxide varistor materials with integrated ceramic packaging technology.

机译:集成陶瓷封装技术的氧化锌压敏电阻材料的兼容性研究。

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摘要

Recent developments in electronics have merged thick film and multilayer ceramic manufacturing techniques to form a new breed of "integrated ceramic" substrates. The goal of this study was to incorporate multilayer varistors in these devices. This included determining the compatibility of the materials, characterizing the varistor-substrate interface, and demonstrating an operational varistor cofired in the substrate. The varistor composition consisted of 98.5 mol% ZnO, 0.5 mol% CoO, and 1 mol% Bi{dollar}sb2{dollar}O{dollar}sb3{dollar}. The substrate used was the DuPont Green Tape substrate.; The sintering study revealed that simple varistor compositions with fine particle sizes will densify at lower temperatures than compositions with coarser particles. This promotes grain growth at lower temperatures, reducing breakdown voltages. Calcining these materials either reduces densification and grain growth, increasing breakdown voltages, or forms aggregates which act as large single grains, reducing breakdown voltages. Samples with cobalt calcined into the ZnO exhibited dramatically reduced nonlinearities, suggesting that cobalt should be left at the grain boundary as electron traps or as hole formation sites. The sintering of coarser calcined materials at lower temperatures is improved if fine materials are added to the composition.; The interfacial study showed that the varistor material forms a continuous bond to the substrate material. The interfacial region consists of three zones: (1) a layer of zinc silicate (willemite) bonding to the ZnO surface, (2) a reaction zone containing ZnAl{dollar}sb2{dollar}O{dollar}sb4{dollar} (gahnite) crystals and (Ca,K)AlSi{dollar}sb3{dollar}O{dollar}sb8{dollar} (feldspar) crystals, bonded by a Bi-Si rich amorphous phase, and (3) a zone where bismuth-rich liquid infiltrates the substrate. Liquid bismuth from the varistor attacks the glass first, but eventually dissolves all of the substrate's components. Electrodes at the interface do not prevent these interactions.; The study of substrate-varistor composites indicated that buried devices could be fabricated between 850 and 950{dollar}spcirc{dollar}C. Excess thickness shrinkage and reduced lateral shrinkage were observed in the composite laminates, caused by early densification of the interface. This constrains the lateral dimensions of the composite and forces the increased thickness shrinkage. The buried varistor contained large amounts of porosity, reducing grain growth and increasing breakdown voltage. Insulation resistances were low in samples containing internal electrodes, suggesting localized grain growth. Nonlinearity coefficients of approximately 15 were observed for the buried devices.
机译:电子学的最新发展已经融合了厚膜和多层陶瓷制造技术,形成了一种新型的“集成陶瓷”基板。这项研究的目的是在这些器件中集成多层压敏电阻。这包括确定材料的兼容性,表征压敏电阻与衬底的界面以及演示在衬底中共烧的工作压敏电阻。压敏电阻成分由98.5mol%的ZnO,0.5mol%的CoO和1mol%的Bi {dollar} sb2 {dollar} O {dollar} sb3 {dollar}组成。使用的基材是杜邦绿色胶带基材。烧结研究表明,与具有较粗颗粒的组合物相比,具有细颗粒尺寸的简单压敏电阻组合物将在较低的温度下致密化。这促进了较低温度下晶粒的生长,降低了击穿电压。煅烧这些材料可减少致密化和晶粒长大,增加击穿电压,或形成聚集体,充当大的单个晶粒,从而降低击穿电压。钴煅烧成ZnO的样品显示出大大降低的非线性,表明钴应留在晶界作为电子陷阱或空穴形成部位。如果在组合物中加入细料,则可改善粗煅烧料在较低温度下的烧结。界面研究表明,压敏电阻材料与基材形成了连续的结合。界面区域由三个区域组成:(1)一层与ZnO表面结合的硅酸锌(硅锌矿)层;(2)含有ZnAl {dol} sb2 {dol}} {{s} b4 {dol} )晶体和(Ca,K)AlSi {dollar} sb3 {dollar} O {dollar} sb8 {dollar}(长石)晶体,由富含Bi-Si的非晶相键合,以及(3)富含铋的液体的区域渗入底物。来自压敏电阻的液体铋首先侵蚀玻璃,但最终溶解了所有衬底成分。界面处的电极不会阻止这些相互作用。对基底-压敏电阻复合材料的研究表明,可以在850至950℃之间制造掩埋器件。由于界面的早期致密化,在复合层压板中观察到了过度的厚度收缩和横向收缩的减少。这限制了复合材料的横向尺寸并迫使厚度收缩增加。埋入的压敏电阻包含大量孔隙,从而减少了晶粒的生长并增加了击穿电压。包含内部电极的样品的绝缘电阻低,表明局部晶粒生长。对于掩埋器件,观察到约15的非线性系数。

著录项

  • 作者

    Nies, Craig William.;

  • 作者单位

    The Pennsylvania State University.;

  • 授予单位 The Pennsylvania State University.;
  • 学科 Engineering Materials Science.; Engineering Electronics and Electrical.; Engineering Packaging.
  • 学位 Ph.D.
  • 年度 1989
  • 页码 224 p.
  • 总页数 224
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;无线电电子学、电信技术;包装工程;
  • 关键词

  • 入库时间 2022-08-17 11:50:40

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