Achieving high performance and energy efficiency in superpipelined processors.

摘要

One approach to exploring instruction-level parallelism is superpipelining which uses deep pipelines to achieve high clock rates. Pipeline hazards, memory latency, and power consumption are three vital factors that limit the benefits of superpipelining. This dissertation presents several novel approaches to achieve high-performance and energy-efficient superpipelined microprocessors. These approaches focus mainly on reducing pipeline stalls, memory latency, and energy consumption of unnecesary bit switches.;To reduce the number of pipeline stalls, an optimizing instruction scheduler, named Super-reorderer, was built in which in-block scheduling and cross-block scheduling are applied to minimize the number of data and structural hazards. A novel branch scheme is proposed, called branch with masked squashing, to minimize the number of control hazards. The basic idea of branch with masked squashing is to fill delay slots with safe instructions which may come before or after the branch. For the remaining unfilled delay slots, instructions from the predicted target path are used to fill the delay slots. In the case of misprediction, only unsafe instructions are annulled. The safe instructions in branch delay slots are always executed.;To reduce memory latency, unconventional cache mapping functions, hardware-controlled instruction prefetching, and software-controlled data prefetching techniques are investigated. Two novel unconventional cache mapping functions: bit-flipping and segmented bit-selection are proposed and evaluated. A direct-mapped cache with these unconventional cache mapping functions can achieve high hit rates, while maintaining a hit time as fast as a direct-mapped cache with traditional mapping. A novel technique for software-controlled data prefetching is proposed in which the starting data in a data region of a working set is prefetched by software and the subsequence data in the data region is prefetched by hardware. One of the limitations of the software-controlled data prefetching techniques is the execution overhead caused by prefetch instructions. A novel instruction set is proposed in which non-memory-access operations are combined with an optional prefetch operation to effectively eliminate the execution overhead caused by a prefetch instruction. A novel hardware-controlled instruction prefetching technique, called branch correlation-based cache prefetching (BCCP), is proposed. The BCCP, which takes advantage of high branch prediction accuracies of correlation-based cache prediction and aggressive cache line look ahead prefetching, is able to effectively hide long instruction cache latency.;To reduce energy consumption in a modern instruction set processor, several novel hardware and software techniques are investigated. A software technique, called Cold Scheduling, is proposed to reduce energy consumption in the control path. The basic idea is to apply compilation techniques to reorder instruction sequences such that the amount of bit switching on the control path is minimal during program execution. Dynamic power management, which automatically shuts down power consumption in unused functional units during program execution, is investigated to reduce energy consumption in the data path. Two novel cache design techniques are proposed, namely Gray code addressing and cache partitioning, to reduce energy consumption in the caches. The idea of the Gray code addressing is to minimize the bit switches on address buses and I/O pads which usually consume a significant amount of energy in the caches. The idea of cache partitioning is to minimize average energy consumption in each cache access by vertically or horizontally partitioning cache memory cell arrays. (Abstract shortened by UMI.)