Design tradeoffs for noise control in signal integrity for MOS-based interconnect systems.

摘要

Three design tradeoff relations for noise control, namely control for ground bounce noise, control for crosstalk noise, and control for reflection noise, in signal integrity for MOS-based systems are discussed here.; Quantitative expressions relating driver size, loading capacitance, edge speed of input signal, parasitic inductance, and a maximum number of allowable simultaneously switching drivers to the worst-case, maximum ground bounce and the signal switching (delay) time are shown to agree with SPICE simulations for both MOS1 and MOS3 devices.; Dependent upon the strength of line coupling, two design guidelines to design interconnect systems for targets of 4% far-end overshoot, 10% far-end crosstalk, and a pre-specified far-end response time are introduced to upgrade package performance and packaging density. To estimate the signal delay time, a simple expression that combines the propagation delay time and the far-end {dollar}Zsb0Csb{lcub}L{rcub}{dollar} time is formulated first. The Elmore delay time for a single line provides a good delay estimate for a signal propagating on loosely coupled lines. For strongly coupled lines, a modified Elmore delay time with a coupling factor is derived, which agrees well with SPICE calculations.; Based upon the assumption that both unscaled and scaled systems satisfy the proposed design guidelines, possible scaling tradeoffs for down-sized (scaled) systems also are examined extensively.