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Design and implementation of a multicast, input-buffered ATM switch for theiPOINT testbed.

机译:iPOINT测试平台的多播输入缓冲ATM交换机的设计和实现。

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This thesis presents the design and implementation of the multicast, input-buffered Asynchronous Transfer Mode (ATM) switch for use with the iPOINT testbed. The input-buffered architecture of this switch is optimal in terms of the memory bandwidth required for the implementation of an ATM queue module. The contention resolution algorithm used by the iPOINT switch supports atomic multicast, enabling the simultaneous delivery of ATM cells to multiple output ports without the need for recirculation buffers, duplication of cells in memory, or multiple clock cycles to transfer a cell from an input queue module.; The implementation of the prototype switch is unique in that it was entirely constructed using Field Programmable Gate Array (FPGA) technology. A fully functional, five-port, 800 Mbps ATM switch has been developed and currently serves as the high-speed, optically interconnected, local area network for a cluster of Sun SPARCstations and the gateway to the wide-area Blanca/XUNET gigabit testbed. Through the use of FPGA technology, new hardware-based switching algorithms and functionality can be implemented without the need to modify hard-wired logic. Further, through the use of the remote switch manager, switch controller, and FPGA controller, the management, operation, and even logic functionality of the iPOINT testbed can be dynamically altered, all without the need for physical access to the iPOINT hardware.; Based on the existing prototype switch, the design of the FPGA-based, gigabit-per-second "Any-Queue" module is presented. For this design in its maximum configuration, up to 256 queue modules can be supported, providing an aggregate throughput of 180 Gbps. Further, the design of a 16-port, 11.2 Gbps aggregate throughput, switch fabric is documented that can be entirely implemented using only eight FPGA devices.; In addition to the design of the switch module, this thesis describes the supporting components of the iPOINT testbed, including the network control and application software, the hardware specifications of the switch interface, and the device requirements of the optoelectronic computers used in the testbed
机译:本文介绍了用于iPOINT测试平台的多播输入缓冲异步传输模式(ATM)交换机的设计和实现。就实现ATM队列模块所需的内存带宽而言,此交换机的输入缓冲体系结构是最佳的。 iPOINT交换机使用的争用解决算法支持原子多播,从而可以将ATM信元同时传送到多个输出端口,而无需再循环缓冲区,内存中信元重复或从输入队列模块传输信元的多个时钟周期。;原型交换机的实现是独特的,因为它完全使用现场可编程门阵列(FPGA)技术构造而成。已经开发出一种功能齐全的五端口800 Mbps ATM交换机,当前它用作Sun SPARCstation集群以及通往广域Blanca / XUNET千兆测试平台的网关的高速,光互连的局域网。通过使用FPGA技术,可以实现新的基于硬件的交换算法和功能,而无需修改硬连线逻辑。此外,通过使用远程交换机管理器,交换机控制器和FPGA控制器,可以动态更改iPOINT测试平台的管理,操作甚至逻辑功能,而无需物理访问iPOINT硬件。基于现有的原型交换机,提出了基于FPGA的每秒千兆比特“ Any-Queue”模块的设计。对于此设计的最大配置,最多可支持256个队列模块,提供180 Gbps的总吞吐量。此外,记录了16端口,11.2 Gbps聚合吞吐量交换结构的设计,该结构可以仅使用八个FPGA器件即可完全实现。除了交换模块的设计之外,本文还介绍了iPOINT测试平台的支持组件,包括网络控制和应用软件,开关接口的硬件规格以及测试平台中使用的光电计算机的设备要求。

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