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On-chip signal processing for CMOS active pixel image sensors.

机译:CMOS有源像素图像传感器的片上信号处理。

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摘要

Desirable performance of low cost, low power and low physical volume and mass for complete camera systems relies on on-chip integration of signal processing circuits. One part of this dissertation focuses on the development of low power, high speed analog-to-digital converters (ADC) for on-chip video signal processing in CMOS digital-camera-on-a-chip systems. The second part of the dissertation is a demonstration of CMOS active pixel image sensors (APS) with customized functionality through on-chip integration of analog signal processing circuits.; On-chip integration of column-parallel successive-approximation ADCs was demonstrated for the first time with good accuracy and ultra-low power consumption. Two charge-scaling ADCs achieved 8-bit resolution at up to 50 ksamples/s conversion rate and less than 150 {dollar}mu{dollar}W power consumption, one of them operates up to 833 ksamples/s with 5-bit resolution. A switched-capacitor ADC using a single inverter amplifier and most compact cell design demonstrated 7-bit resolution at up to 55 ksamples/s. The first APS sensor with column-parallel successive-approximation ADCs demonstrated 8-bit resolution images up to 4 Mpixels/s, the highest readout rate so far with column-parallel ADCs. Digital imaging devices for commercial video applications and high speed industrial applications can be developed based on these ADC designs.; Two integrating CMOS sensors with pixel binning and one of them, frame transfer capability were demonstrated for the first time. A 32 x 32 element sensor with single-ended column circuits achieved 50 dB dynamic range, 1.58 mW power consumption at 400 Hz frame rate and 1.5% fixed-pattern-noise (FPN) with 1V full signal swing. A 128 x 128 element integration sensor with fully differential column integrator circuits achieved 72 dB dynamic range, 24 mW power consumption at 125 Hz frame rate and 0.5% FPN with 1.2 V full signal swing. The integration APS sensors have applications in time delay integration (TDI) imaging and light level adaptive imaging. Successful integration of these column circuits paved a road for on-chip integration of other analog circuits based on column-parallel operational amplifiers and integrators.; Work presented in this dissertation demonstrated the column-parallel implementation as a feasible approach for on-chip signal processing with low power consumption and good performance.
机译:对于完整的相机系统而言,低成本,低功耗,低物理体积和低质量的理想性能取决于信号处理电路的片上集成。本文的一部分着重于低功耗,高速模数转换器(ADC)的开发,以用于CMOS数码相机芯片系统中的片上视频信号处理。论文的第二部分是通过对模拟信号处理电路进行片上集成来演示具有定制功能的CMOS有源像素图像传感器(APS)的演示。首次演示了列并行逐次逼近型ADC的片上集成,具有良好的精度和超低功耗。两个电荷缩放ADC达到8位分辨率,转换速率高达50 ksamples / s,功耗低于150 {μm}美元,其中一个以5位分辨率运行高达833 ksamples / s。使用单个逆变器放大器和最紧凑的单元设计的开关电容器ADC展示了高达55 ksamples / s的7位分辨率。第一个具有列并行逐次逼近型ADC的APS传感器展示了高达4 Mpixels / s的8位分辨率图像,这是列并行ADC迄今为止的最高读取率。基于这些ADC设计,可以开发用于商业视频应用和高速工业应用的数字成像设备。首次展示了两个集成有像素合并功能的CMOS传感器,其中一个具有帧传输功能。具有单端列电路的32 x 32元素传感器实现了50 dB的动态范围,在400 Hz帧频下的功耗为1.58 mW,具有1V全信号摆幅的1.5%固定模式噪声(FPN)。具有全差分列积分器电路的128 x 128元素积分传感器实现了72 dB的动态范围,125 Hz帧速率下的24 mW功耗和0.5%FPN(1.2 V全信号摆幅)。集成APS传感器在时延集成(TDI)成像和光照水平自适应成像中具有应用。这些列电路的成功集成为基于列并行运算放大器和积分器的其他模拟电路的片上集成铺平了道路。本文的工作证明了列并行实现是一种可行的,具有低功耗和良好性能的片上信号处理方法。

著录项

  • 作者

    Zhou, Zhimin.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1997
  • 页码 260 p.
  • 总页数 260
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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