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Switching and error recovery in terabit ATM networks.

机译:太比特ATM网络中的交换和错误恢复。

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摘要

This thesis addresses two of the main issues required to build reliable terabit ATM networks. A high-capacity switch and an efficient error recovery protocol are the key elements in building a reliable terabit ATM network. In this thesis, a terabit switch architecture and a reliable end-to-end error recovery protocol for terabit networks are introduced.; The proposed terabit ATM switch architecture is designed to work efficiently in low-capacity and high-capacity environments. The architecture is developed by interconnecting small-capacity switching modules in a scalable fashion. The switching module can be used alone as a small-capacity ATM switch. Multiple the switching modules can be used to achieve any required switching capacity. The proposed interconnecting scheme provides remarkable low cell-delay characteristics with a simple distributed cell scheduler. The proposed architecture has a high reliability: Even when a complete switching module fails the switch will continue to work efficiently.; The switching element which is introduced as the main building block for the terabit switch architecture is a nonblocking input buffer ATM switch. The input buffers are implemented as groups of parallel shift-registers. The parallel nature of the storing buffers overcomes the Head Of Line and low throughput problems of existing input buffer switch architectures. In addition, using the shift registers overcomes the need for serial-to-parallel and parallel-to-serial format conversions.; ATM networks support different types of services having different delay and loss requirements. A priority scheduling scheme is proposed to facilitate the support of different Qualities of Service. The proposed scheme satisfies both real-time and non-real-time service requirements.; Cell loss is not acceptable for some data applications. This thesis proposes an efficient error recovery protocol which guarantees reliable communication with limited overhead. The proposed protocol requires a low number of control packets to achieve reliable communication. It also adapts itself, in order to work efficiently during both congested and non-congested states.
机译:本论文解决了构建可靠的太比特ATM网络所需的两个主要问题。大容量交换机和有效的错误恢复协议是构建可靠的太比特ATM网络的关键要素。本文介绍了太比特网络的太比特交换体系结构和可靠的端到端错误恢复协议。拟议的太比特ATM交换机体系结构旨在在低容量和高容量环境中有效工作。通过以可扩展的方式互连小容量交换模块来开发该体系结构。交换模块可以单独用作小容量ATM交换机。多个交换模块可用于实现任何所需的交换容量。所提出的互连方案利用简单的分布式小区调度器提供了显着的低小区延迟特性。所提出的体系结构具有很高的可靠性:即使当完整的交换模块发生故障时,交换器仍将继续有效地工作。作为太比特交换机体系结构的主要构建模块引入的交换元素是无阻塞输入缓冲区ATM交换机。输入缓冲器被实现为并行移位寄存器组。存储缓冲区的并行性质克服了现有输入缓冲区切换体系结构的行首和低吞吐量问题。另外,使用移位寄存器可以消除串行到并行和并行到串行格式转换的需要。 ATM网络支持具有不同延迟和丢失要求的不同类型的服务。提出了优先级调度方案,以促进对不同服务质量的支持。拟议的方案同时满足实时和非实时服务要求。对于某些数据应用程序,信元丢失是不可接受的。本文提出了一种有效的错误恢复协议,该协议可以在有限的开销下保证可靠的通信。所提出的协议需要少量的控制分组以实现可靠的通信。它还可以自我调整,以便在拥塞和非拥塞状态下均能高效工作。

著录项

  • 作者

    Sabaa, Amr Gaber.;

  • 作者单位

    University of Victoria (Canada).;

  • 授予单位 University of Victoria (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1999
  • 页码 136 p.
  • 总页数 136
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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