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Stress effects on electrostatic potential barriers in piezoelectric semiconductors.

机译:应力对压电半导体中的静电势垒的影响。

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摘要

Electrically active interfaces are integral to and often dictate solid state device properties. These interfaces are engineered with ever greater complexity and precision to yield improved electronics and novel classes of devices. In the case of polycrystalline semiconductors, the materials can be fabricated into bulk devices through ceramic processing routes, and the electrical behavior may be strongly dependent on electrostatic potential barriers at the grain boundaries. Zinc oxide varistors represent a commercially successful example of these electroceramics. ZnO, as with all tetrahedrally coordinated compound semiconductors, is piezoelectric owing to its lack of a center of symmetry. The present work aims to establish the effects of stress on grain boundary potentials as coupled through the piezoelectric effect.; First, a stochastic model is presented which addresses piezoelectric modifications of barrier heights in polycrystalline ZnO. The change in macroscopic transport behavior is correlated to the influence of an internal stress distribution on the barrier height distribution via these modifications. It was found that a broadening of the stress distribution causes a degradation in varistor switching behavior.; This work motivated a study of epitaxial ZnO film growth for constructing bicrystalline varistors. Though it was not possible to control the morphology to an extent amenable for grain boundary investigations, a model was developed to explain the evolution of morphologies observed. In a kinetically limited growth regime, c axis oriented ZnO exhibits a “cratered” surface topography due to geometrical growth and lateral impingement of hexagonal pyramids. As elucidated by the model, the resultant surface morphology suggests a probabilistic distribution of nuclei in both time and space, with facetting of the crater dictated by the in-plane orientation distribution of the crystallites.; Lastly, in an attempt to investigate the interaction of piezoelectric charges and the potential barrier at a well defined, flat boundary, the effects of stress on GaN Schottky diodes were explored. The diode behavior was seen to weakly depend on stress, suggesting that piezoelectric charges are neutralized by the metal rather than by charge redistribution in the semiconductor.
机译:电有源接口是固态设备特性不可或缺的,通常决定着固态设备的特性。这些接口的工程设计越来越复杂,精度越来越高,可以生产出改进的电子产品和新颖的设备类别。在多晶半导体的情况下,可以通过陶瓷加工路线将材料制成块状器件,并且电性能可能强烈依赖于晶界处的静电势垒。氧化锌压敏电阻代表了这些电陶瓷的商业成功实例。与所有四面体配位化合物半导体一样,ZnO由于缺乏对称中心而成为压电材料。本工作旨在通过压电效应建立应力对晶界电势的影响。首先,提出了一种随机模型,用于解决多晶ZnO中势垒高度的压电变化。通过这些修改,宏观传输行为的变化与内部应力分布对势垒高度分布的影响相关。已经发现,应力分布的加宽导致压敏电阻开关性能的降低。这项工作激发了研究外延ZnO薄膜生长以构建双晶压敏电阻的研究。尽管不可能将晶形控制到适合晶界研究的程度,但还是开发了一个模型来解释观察到的形貌的演变。在动力学受限的生长方式中,由于六方锥的几何生长和横向撞击,c轴取向的ZnO呈现出“凹陷”的表面形貌。如模型所阐明的,所得的表面形态表明原子核在时间和空间上均具有概率分布,而弹坑的刻面由微晶的面内取向分布决定。最后,为了研究压电电荷与势垒在明确界定的平坦边界上的相互作用,探讨了应力对GaN肖特基二极管的影响。可以看到二极管的行为在一定程度上取决于应力,这表明压电电荷被金属中和,而不是被半导体中的电荷重新中和。

著录项

  • 作者

    Verghese, Paul Mattackal.;

  • 作者单位

    University of California, Santa Barbara.;

  • 授予单位 University of California, Santa Barbara.;
  • 学科 Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 1999
  • 页码 94 p.
  • 总页数 94
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;
  • 关键词

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