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Physical modeling and characterization of submicron SOI and bulk MOSFET devices.

机译:亚微米SOI和体MOSFET器件的物理建模和表征。

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摘要

A four-terminal physical subcircuit model for FB partially depleted (PD) and near fully depleted (nearFD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (Vds) induced floating-body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in nearFD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.; A simple analytical threshold voltage model for short-channel fully depleted (FD) SOI MOSFETs has been derived. The model is based on the analytical solution of the two dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential (SISP) at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work.; A modified Berkeley short-channel IGFET model (BSIM1) has been developed to accurately model the I-V characteristics and circuit performance of deep submicron MOSFET devices. The improved model provides a simple and more efficient parameter acquisition procedure for MOSFET global modeling in comparison to the original BSIM1 model. (Abstract shortened by UMI.)
机译:提出了一种四端物理子电路模型,用于FB部分耗尽(PD)和 near 完全耗尽( near FD)SOI CMOS器件。该模型考虑了与漏极引起的浮体效应相关的PD设备的独特特性。 V ds 与其他模型不同,所提出的电路模型从物理上考虑了后MOSFET器件,并准确预测了 near FD器件中电流扭结的偏置依赖性。它允许适当的电容缩放以及与正面和背面氧化物/通道有关的更准确的模拟。还包括与背氧化层的低导热率有关的自热效应。该电路模型与SPICE兼容,可提供洞察力,以了解对高性能的最佳器件设计需求。描述了一种提取模型参数的简单技术。仿真结果与实验数据吻合良好,验证了模型的正确性。电路级仿真实例支持了子电路模型的预测能力。推导了一种用于短沟道全耗尽(FD)SOI MOSFET的简单分析阈值电压模型。该模型基于硅膜(正面硅)中二维电势分布的解析解,该解析解被用作泊松方程的长通道解和拉普拉斯方程的短通道解之和,以及在硅基板(背面硅)中的泊松方程的解。提出的模型考虑了在掩埋的氧化物-衬底界面处的背栅衬底感应表面电势(SISP)的影响,这为该工作中使用的器件的阈值电压贡献了额外的15-30%的降低。已开发出一种改进的伯克利短沟道IGFET模型(BSIM1),以精确地模拟深亚微米MOSFET器件的I-V特性和电路性能。与原始的BSIM1模型相比,改进后的模型为MOSFET全局建模提供了一种简单而有效的参数获取程序。 (摘要由UMI缩短。)

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