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High-speed CMOS continuous-time switched-current sigma-delta modulators.

机译:高速CMOS连续时间开关电流sigma-delta调制器。

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摘要

Oversampling SigmaDelta analog-to-digital converters (ADC) trade analog accuracy for digital complexity and are preferred for CMOS technology due to their high resolutions and less analog accuracy requirement. In the past, implementations of oversampling SigmaDelta ADCs have been dominated by switched-capacitor (SC) circuits. Due to the limitations of settling requirement, internal feedback, and signal-dependent sampling errors, switched-capacitor SigmaDelta ADCs can sample only at the rate of a few tens of MHz. Although advanced CMOS processes offer higher and higher fT for MOS transistors, conventional oversampling SigmaDelta analog-to-digital converters cannot benefit from these advantages.; This research proposes a new architecture for realizing high speed SigmaDelta modulators (the analog part of oversampling SigmaDelta ADCs). With the use of continuous-time open-loop integrators for loop filters and current switches as digital-to-analog converters (DACs) in the feedback paths, the proposed continuous-time switched-current SigmaDelta modulator can operate at much higher sampling rates then its switched-capacitor counterpart.; Nevertheless, the implementation of high-speed continuous-time switched-current SigmaDelta modulators involves several circuit design challenges, including switching noise, background noise, clock jitter, excessive loop delay, loop gain variation, etc. This research has successfully solved these problems with newly designed architectures and building blocks. With the differential structures and differential current switches, the noise problem was solved to enable the modulator to operate at high speeds. The proposed common-mode feedback circuits and high-speed current comparator enhance the performance of the modulator. The stability problems have been solved with new structures for delay compensation and by the use of feedforward gain compensation with a Gain Manager.; Prototypes of these modulator have achieved a 50MHz sampling rate for a 2mum process and a 400MHz sampling rate for a 0.6mum process, which are much higher than their switched-capacitor counterparts. The experimental results of this research have proven the superiority of continuous-time switched-current SigmaDelta modulators in high-speed sampling. The properties of higher bandwidth, no input sampling, less KT/C thermal noise, and insensitivity to clock jitter also enable continuous-time switched-current SigmaDelta modulators to track advances in CMOS technology.
机译:过度采样SigmaDelta模数转换器(ADC)以模拟精度代替数字复杂度,并且由于其高分辨率和较少的模拟精度要求,因此首选CMOS技术。过去,过采样SigmaDelta ADC的实现方式主要由开关电容器(SC)电路主导。由于建立要求,内部反馈和与信号有关的采样误差的限制,开关电容器SigmaDelta ADC只能以几十MHz的速率进行采样。尽管先进的CMOS工艺为MOS晶体管提供了越来越高的fT,但是传统的过采样SigmaDelta模数转换器无法从这些优势中受益。这项研究提出了一种用于实现高速SigmaDelta调制器(过采样SigmaDelta ADC的模拟部分)的新架构。通过在反馈路径中将连续时间开环积分器用于环路滤波器和电流开关作为数模转换器(DAC),建议的连续时间开关电流SigmaDelta调制器可以以比现在高得多的采样率工作其开关电容器对应物。然而,高速连续时间开关电流SigmaDelta调制器的实现涉及多个电路设计挑战,包括开关噪声,背景噪声,时钟抖动,过大的环路延迟,环路增益变化等。这项研究成功解决了这些问题:新设计的架构和构建块。利用差分结构和差分电流开关,噪声问题得以解决,从而使调制器能够高速运行。所提出的共模反馈电路和高速电流比较器提高了调制器的性能。新的延迟补偿结构和增益管理器使用前馈增益补偿解决了稳定性问题。这些调制器的原型在2μm的过程中实现了50MHz的采样率,在0.6mum的过程中实现了400MHz的采样率,远高于其开关电容器同类产品。这项研究的实验结果证明了连续时间开关电流SigmaDelta调制器在高速采样中的优越性。更高的带宽,无需输入采样,更少的KT / C热噪声以及对时钟抖动不敏感的特性也使连续时间开关电流SigmaDelta调制器能够跟踪CMOS技术的发展。

著录项

  • 作者

    Luh, Louis.;

  • 作者单位

    University of Southern California.;

  • 授予单位 University of Southern California.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2000
  • 页码 102 p.
  • 总页数 102
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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