Register-transfer level fault modeling and test evaluation technique for VLSI circuits.

摘要

Test patterns for large VLSI systems are often determined from the knowledge of the circuit function. A fault simulator is then used to find the effectiveness of the test patterns in detecting gate-level “stuck-at” faults. Existing gate-level fault simulation techniques suffer prohibitively expensive performance penalties when applied to the modern VLSI systems of larger sizes. Also, post-synthesis findings of such test generation and fault simulation efforts are too late in the design cycle to be useful for Design-For-Test (DFT) related improvements in the architecture. Therefore, an effective Register-Transfer Level (RTL) fault model is highly desirable.; In this thesis, a novel procedure that supports RTL fault simulation and generates an estimate of the gate-level fault coverage for a given set of test patterns is proposed. This procedure is based on new RTL fault model, fault-injection algorithm application of stratified sampling theory, and stratum weight extraction techniques. The VLSI system consists of interconnections of modules described in an RTL language. The proposed RTL fault model and the fault-injection algorithm are developed such that the RTL fault-list of a module becomes a representative sample of the collapsed gate-level fault-list. In other words, the RTL faults of a module have a distribution of detection probabilities similar to that of the collapsed gate-level faults. The RTL fault coverage of the proposed fault model tracks the gate-level fault coverage within error bounds predicted by the random sampling technique. An application of the stratified sampling theory supports RTL fault modeling for VLSI systems that consist of interconnected modules. The RTL fault coverages of all modules in a VLSI system are added according to their respective stratum weights as per the stratified sampling theory, Several stratum weights extraction techniques are developed to support the application of the stratified sampling theory to the RTL fault modeling for VLSI systems. The stratified RTL fault coverage serves as an estimate of the gate-level fault coverage of the VLSI system within statistical error bounds.; Performing fault simulation at the RT level using the proposed procedure has several advantages: (a) a significant performance gain in fault simulation compared to the prevailing gate-level approach, (b) the possibility of improving tests prior to logic synthesis, and (c) the early detection of testability problems enabling design for testability in the pre-synthesis phase of the VLSI design cycle. These significant advantages give the proposed procedure potential for application.