Performance optimization methodologies for design of digital VLSI systems.

摘要

Our primary objective in this research has been to study novel approaches for performance optimization of digital VLSI systems. Performance of VLSI systems is characterized by three main parameters, the speed of operation, the area of the implementation and the average power expended per computation. Depending on the application under investigation some or all of these parameters are of paramount importance. We have investigated novel approaches that target all of the above for general VLSI systems and in particular we will look at Digital Signal Processing (DSP) applications. These applications are ever pervading in present day-to-day life since DSP is required in basic amenities such as cell-phones, television and in medical applications like an Electro Cardio Gram (ECG) recording device. VLSI systems exist in several levels of hierarchy, from the topmost system level, to the bottommost physical level. The design issues at various levels have different flavors but the ultimate objective for a designer at all levels is some kind of performance optimization. As a part of this research we have studied performance optimization strategies for minimal area Discrete Wavelet Transforms were derived that showed a 25% reduction in area of implementation over existing approaches. Also at architecture level, synthesis techniques for low power FIR filters were also proposed which led to 80% lower power consumption over traditional filter synthesis approaches. Insights obtained from the above technique were then used to design a Multiplier Multiple Accumulator (MMAC) component for use in Programmable Digital Signal Processors (PDSPs) for low power mappings of FIR filters. At system level, strategies to lower power consumption in busses were developed that resulted in up to 21.88% power savings over traditional bus implementation strategies. In addition the data-transmission rate on these busses is up to 20% higher than existing techniques for a given savings in power. At logic level area/speed optimization with retiming while incorporating setup and hold constraints was developed for the first time. At transistor level, transistor level optimization was studied for the delay constrained, minimum area transistor sizing problem. The technique studied here was optimal and showed remarkable run-time behavior improving the state of the art for this application. For example a circuit with 3512 sizable elements was sized in 363s in an Ultra-sparc10 computer. Finally also, at logic gate level power optimization with gate resizing, multiple supply voltages, and multiple threshold voltages were developed which showed substantial improvement over existing techniques.