首页> 外文学位 >Dependable computing techniques for reconfigurable hardware.
【24h】

Dependable computing techniques for reconfigurable hardware.

机译:可重构硬件的可靠计算技术。

获取原文
获取原文并翻译 | 示例

摘要

Reconfigurable hardware, such as Field-Programmable Gate Arrays (FPGAs), has become a very important component in various applications, including communication networking, and storage systems. With the re-programmable feature and a tremendous increase in on-chip logic and routing resources, contemporary reconfigurable hardware also opens new opportunities in designing dependable systems with fine-grained hardware redundancy.; In traditional dependable systems using hardware redundancy, fault tolerance is realized by replicating functional modules at the level of a chip or a board. Such coarse-grained hardware redundancy is very expensive. In reconfigurable hardware, however, a more cost-effective method is made possible by using an alternative configuration in which the faulty parts are replaced with originally unused resources in the same device.; Dependable computing using reconfigurable hardware requires three layers of support. First, Concurrent Error Detection (CED) is required in order to guarantee the correctness of outputs and detect errors. Second, transient error recovery is needed to restore normal operations from failures due to temporary environmental disturbances. Third, permanent fault recovery, including fault location techniques and reconfiguration strategies for tolerating permanent faults, is required to repair a system with physical failures in the hardware. Since these techniques are executed at run-time, it is desired to minimize their performance impact and to ensure high availability.; We investigate the issues in each layer of support for dependable computing in reconfigurable hardware. For CED techniques, we present the inverse comparison scheme suitable for applications with unique inverses. For transient error recovery, we examine a memory coherence issue in the recovery process and present a dirty-bit memory coherence technique with low execution time overhead. For permanent fault recovery, we present an integrated scheme using the column-based precompiled configuration technique for repair and the blind reconfiguration approach for fault location. Our techniques ensure very fast and cost-effective fault recovery in reconfigurable, hardware
机译:可重配置的硬件,例如现场可编程门阵列(FPGA),已经成为包括通信网络和存储系统在内的各种应用程序中非常重要的组件。借助可重新编程的功能以及片上逻辑和路由资源的大量增加,现代可重新配置的硬件也为设计具有细粒度硬件冗余的可靠系统提供了新的机会。在使用硬件冗余的传统可靠系统中,容错通过在芯片或板级复制功能模块来实现。这种粗粒度的硬件冗余非常昂贵。但是,在可重新配置的硬件中,通过使用另一种配置,使故障部件替换为同一设备中本来未使用的资源,可以实现一种更具成本效益的方法。使用可重配置硬件的可靠计算需要三层支持。首先,需要并发错误检测(CED),以确保输出的正确性并检测错误。其次,需要暂时的错误恢复来使正常的操作恢复到由于暂时的环境干扰而导致的故障。第三,需要永久故障恢复,包括故障定位技术和用于容忍永久故障的重新配置策略,以修复硬件中出现物理故障的系统。由于这些技术是在运行时执行的,因此希望最大程度地降低其性能影响并确保高可用性。我们调查可重构硬件中对可靠计算的每个支持层中的问题。对于CED技术,我们提出了适用于具有唯一逆的应用程序的逆比较方案。对于瞬态错误恢复,我们检查了恢复过程中的内存一致性问题,并提出了一种具有低执行时间开销的脏位内存一致性技术。对于永久性故障恢复,我们提出了一种集成方案,该方案使用基于的基于列的预编译配置技术进行修复,并使用 blind reconfiguration 方法进行故障定位。我们的技术可确保在可重新配置的硬件中实现非常快速且经济高效的故障恢复

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号