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Advanced Channel Engineering for Thin Body Transistors.

机译:薄体晶体管的高级通道工程。

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摘要

As transistor dimension kept scaling down, many challenges arises such as worse electrostatic control and higher variability. In order to address these issues, thin down body thickness is widely accepted and device structures such as FinFET and SOI are employed. Although FinFET has been adopted as main device structure by major foundries like Intel and TSMC in 20nm node and beyond, its analog performances like gm and fT are still lagging behind the bulk and SOI and prevent it from applying to SOC applications. In order to maintain the scaling trend, new materials and/or novel device design is needed. Therefore, channel engineering by using laterally composed with different electron affinities along the channel is proposed to show improved analog performance.;Besides thinning down body thickness, there are other methods to realize thin body and one of them is applying channel engineering by employing deeply retrograde doping profile (DRCP) in bulk device. The doping profile is designed such that it behaves like a thin body device while maintaining bulk device structure. The advantage of DRCP device is that it is relatively cheap and less complicated in terms of manufacturing than those device structures with physically thinner silicon body like FinFET and SOI. It is then instructive to understand whether DRCP device can deliver comparable device performance as FinFET and SOI in 20nm regime. The physics of DRCP device is investigated by TCAD simulation tools and compared with halo device (conventional bulk device) to show the origin of the superior performance. The device performances of bulk device, DRCP, FinFET and SOI are compared to show the capability of DRCP device.;The other approach to make thin body is to utilize 2D materials like transition metal di-chalcogenides (TMDs) as channel material of transistor owning to its ultra-thin body property. 2D materials such as MoS2 and WSe 2 were extensively exploited recently for FET fabrication due to the good short channel effect control and potential superior carrier transport. Among these 2D materials, WSe2 is particularly attractive since p-type doping has been achieved making it possible for depletion mode p-FET. However, lack of reliable doping technique makes the doping of the WSe 2 difficult to be accomplished. In this dissertation, WSe2 doped by controllable W:Ta co-sputtering process and synthesized by post selenization is demonstrated. The material synthesis and characterization of WSe2 are discussed. The transmission line method (TLM) structure is used to extract the sheet resistance and contact resistance with palladium contact. The MESFET is fabricated and the performance are discussed.
机译:随着晶体管尺寸的不断缩小,出现了许多挑战,例如更差的静电控制和更高的可变性。为了解决这些问题,薄型车身厚度已被广泛接受,并采用了诸如FinFET和SOI之类的器件结构。尽管FinFET已被20nm节点及以后的主要代工厂如Intel和TSMC用作主要设备结构,但其gm和fT之类的模拟性能仍落后于大容量和SOI,并使其无法应用于SOC应用。为了维持缩放趋势,需要新材料和/或新颖的装置设计。因此,提出通过沿沟道使用具有不同电子亲合力的侧向组成的沟道工程来显示改善的模拟性能。除了减薄体厚度之外,还有其他方法来实现薄体,其中一种方法是通过深深逆行来应用沟道工程。批量设备中的掺杂配置文件(DRCP)。掺杂轮廓的设计使其在保持整体器件结构的同时,可以像薄型器件一样工作。 DRCP器件的优点是,与那些具有诸如FinFET和SOI的物理上更薄的硅体的器件结构相比,DRCP器件相对便宜且制造复杂。因此,了解DRCP器件是否可以在20nm制程中提供与FinFET和SOI相当的器件性能具有指导意义。通过TCAD仿真工具对DRCP设备的物理特性进行了研究,并将其与晕轮设备(常规散装设备)进行比较,以证明其优越性能的起源。比较了大容量器件,DRCP,FinFET和SOI的器件性能,以显示DRCP器件的能力。另一种制造薄型体的方法是利用过渡金属双硫族化物(TMD)等2D材料作为晶体管拥有的沟道材料。使其具有超薄的身体特性。由于良好的短沟道效应控制和潜在的优异载流子传输,最近已广泛地将2D材料(例如MoS2和WSe 2)用于FET制造。在这些2D材料中,WSe2特别吸引人,因为已经实现了p型掺杂,从而可以使用耗尽型p-FET。然而,缺乏可靠的掺杂技术使得WSe 2的掺杂难以完成。本文通过可控的W:Ta共溅射工艺掺杂了WSe2,并通过硒化后合成了WSe2。讨论了WSe2的材料合成和表征。传输线方法(TLM)结构用于提取与钯接触的薄层电阻和接触电阻。制造了MESFET并讨论了性能。

著录项

  • 作者

    Chien, Po-Yen.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2016
  • 页码 86 p.
  • 总页数 86
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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