Circuit size and complexity considerations, along with strenuous time-to-market constraints and the emerging core-based design trends, have intensified the importance of hierarchical test methodologies. Hierarchical test employs a divide-and-conquer approach to reduce the size of the test generation problem and improve fault coverage and test generation time, yet at the cost of necessitating access to each module. Module accessibility, however, incurs significant hardware overhead, limiting the cost-effectiveness and applicability of hierarchical test. It is, therefore, essential that accessibility behavior inherently available in the design be exploited as much as possible, before resorting to costly module access hardware.; This research investigates the challenges that need to be addressed in order to achieve cost-effective hierarchical test. Issues discussed are the definition and extraction of transparency behavior for traversing through the design, the construction of low-cost paths for accessing and testing each module, the definition of accurate test requirements for each module and the incorporation of control modules in hierarchical test path construction with minimal cost.; The key finding of this research is that a fine-grained transparency definition, as opposed to previously used word-level approaches, is instrumental to the success of hierarchical test. Despite the complexity of gate-level transparency extraction, a wide class of fine-grained transparency functions may be rapidly derived, based on the principles of transparency decomposition theory. Furthermore, this research finds that unlike previous approaches, wherein coarse test requirements are defined symbolically, a cell-level analysis provides a set of matching, fine-grained requirements adequate for testing each module. Fine-grained test requirement identification and transparency extraction supports construction of exact bitwidth hierarchical test paths, thus eliminating the overhead incurred by coarse, word-level paths. In addition, this research finds that despite the non-transparent nature of controllers, the introduced concept of influence tables allows such modules to be incorporated in hierarchical test path construction without necessarily breaking the controller-datapath interface via expensive hardware, as in previous approaches. Based on these findings, a highly accurate testability analysis methodology is proposed, supporting informed, low-cost testability modifications, and, consequently, cost-effective and highly efficient hierarchical test generation, as compared to gate-level ATPG.
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