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Energy-efficient processor system design.

机译:节能处理器系统设计。

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摘要

Motivated by the pervasive use of general-purpose processors in portable electronics devices, energy-efficient processor system design is presented as a critical enabler for smaller, more powerful, and longer-running devices. A decade of research has demonstrated that extremely energy-efficient ASIC and custom DSP design is achievable, but the energy-efficiency of general-purpose processors has severely lagged behind. Thus, despite only performing a small fraction of the computation in these portable devices, the processor system contributes a significant, if not dominant, fraction of the device's total energy consumption. This thesis introduces and demonstrates a top-down processor system design methodology for dramatically reducing energy consumption, while maintaining the desired level of performance.; By understanding the fundamental usage requirements of a processor in portable devices, combined with analytical models for energy consumption and performance, energy-efficiency metrics are derived. A key design technique derived from these metrics, dynamic voltage scaling, is then described for achieving the single-largest increase in energy-efficiency. The metrics are further utilized in developing an overall energy-conscious design flow methodology, and more specifically, energy-efficient architectural and circuit design methodologies to additionally improve system energy-efficiency.; The design and measured results are reported on a prototype processor system, which successfully demonstrates the design techniques and methodologies presented in this thesis, and the potential improvement in processor system energy-efficiency. The system consists of four custom chips: a microprocessor, an SRAM, a voltage converter, and an I/O interface chip. On top of this system runs a real-time operating system, which executes software programs typically found in portable devices, to demonstrate a complete embedded processor system. This prototype system's energy-efficiency was quantified, and demonstrated to be more than order of magnitude higher than the most energy-efficient processor system available today.
机译:出于在便携式电子设备中普遍使用通用处理器的动机,高能效处理器系统设计被认为是小型,功能强大且运行时间更长的设备的关键推动力。十年的研究表明,可以实现极高能效的ASIC和定制DSP设计,但是通用处理器的能效却严重落后。因此,尽管在这些便携式设备中仅执行一小部分计算,但是处理器系统贡献了设备总能耗的很大一部分(如果不是主要部分)。本文介绍并演示了一种自上而下的处理器系统设计方法,可在保持所需性能水平的同时显着降低能耗。通过了解便携式设备中处理器的基本使用要求,并结合能耗和性能的分析模型,可以得出能效指标。然后描述了从这些指标中得出的关键设计技术,即动态电压缩放,以实现能量效率的最大增长。这些度量标准还用于开发整体的节能设计流程方法,更具体地说,是节能建筑和电路设计方法,以进一步提高系统能效。在一个原型处理器系统上报告了设计和测量结果,它成功地证明了本文提出的设计技术和方法,以及处理器系统能效方面的潜在改进。该系统由四个定制芯片组成:微处理器,SRAM,电压转换器和I / O接口芯片。在该系统之上运行一个实时操作系统,该操作系统执行通常在便携式设备中发现的软件程序,以演示完整的嵌入式处理器系统。该原型系统的能效已被量化,并证明比当今最节能的处理器系统高出多个数量级。

著录项

  • 作者

    Burd, Thomas David.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 292 p.
  • 总页数 292
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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