A 32-word by 32-bit three-port bipolar register file implemented using a silicon germanium HBT BiCMOS technology.

摘要

A 32-word by 32-bit bipolar register file with 2 read ports and 1 write port is described. This register file was implemented using a SiGe heterojunction bipolar transistor (HBT) BiCMOS technology. This technology supports an HBT with an f_T of 48 GHz and an f_max of 69 GHz. A test chip was designed to determine the on-chip register file performance in a pipelined system. Two iterations of the design were fabricated. The two 5-bit counters on the test chip used to generate read addresses operated using average maximum clock frequencies of 4.3 GHz and 5.1 GHz on the first iteration, and 5.8 GHz and 5.0 GHz on the second iteration. The 5-bit counter on the test chip used to generate write addresses operated using an average maximum clock frequency of 4.0 GHz on the second iteration, but did not operate correctly on the first iteration. The 6-bit linear feedback shift register (LFSR) on the test chip used to generate input data operated using an average maximum clock frequency of 5.5 GHz on the second iteration.; The best measured die on the first iteration has a read access time of 330 ps for port A, while the port B read access time is 350 ps, based on four measured columns for each port. The write access time for this register file is unknown, while the estimated power dissipation is 6.8 W using a 5 V supply. Some of the column read access times were much lower than the worst case column access time for a particular die, however, such as the 280 ps read access time on one of the columns of the best measured die on the first iteration. The best measured die on the second iteration has a read access time of 350 ps for port A, while the port Bread access time is 360 ps, again based on four measured columns for each port. This die has a read after write access time of 320 ps for port A, and a read after write access time of 350 ps for port B. The write access time for this register file is 340 ps, with a write enable pulse width of 170 ps, while the estimated power dissipation is 4.7 W using a 4.5 V supply. Some of the column read access times were also much lower than the worst case column access time for a particular die on the second iteration, such as the 290 ps read access time on one of the columns of another measured die on the second iteration.; For the average maximum clock frequency of the read address counters, the simulation results varied between 13% and 35% of the measured results on the first iteration, while on the second iteration, the simulation results varied between 0.3% and 25% of the measured results, depending on the counter and which models were used. For the average maximum clock frequency of the write address counter, the simulation results varied between 44% and 57% of the measured results on the second iteration, depending on which models were used. For the average maximum clock frequency of the data LFSR, the simulation results varied between 52% and 72% of the measured results on the second iteration, again depending on which models were used. For the average read access times, simulation results on the first iteration of the register file were within 8% of the measured results for both ports, while on the second iteration, the simulation results were within 13% of the measured results for both ports. For the average read after write access times, simulation results on the second iteration of the register file varied between 16% and 57% of the measured results, depending on which models and assumptions were used. For the average write access times, simulation results on the second iteration of the register file varied between 6% and 62% of the measured results, also depending on which models and assumptions were used. For the average minimum write enable pulse width, simulation results for the second iteration of the register file varied between 24% and 69% of the measured results, again depending on which models and assumptions were used.