Design of advanced low-power, sub-quarter micron metal oxide semiconductor field effect transistors (MOSFET).

摘要

The need for deep sub-micron low-power MOSFET is driven by the ever-increasing demand from mobile electronic market. The hunger for speed and functionality has driven the MOSFET channel length into the sub 0.1μm regions. In the mean time, the electronic power consumption requirements have remained the same. As MOSFET channel length is shrunk below 0.5μm, the MOSFETs experience sever short channel effects, DIBL and sub-threshold-slope degradation. Fully depleted SOI (FDSOI) MOSFET can attenuate these problems. However at sub 0.25μm region, the drain electrical field penetrates into the channel like a fringing back gate causing unwanted back channel conduction and DIBL. A heavily doped ground plane below the buried oxide has been proven to shield the channel from the drain potential. However, no self-aligned process has been reported. We propose for the first time a self-aligned implanted ground plane FDSOI MOSFET. The self-aligned process starts with dummy nitride gates. Then a PSG layer is deposited and CMPed to the nitride height. The dummy nitride gates are selectively etched to form damascene gate slots in the PSG layer. The ground plane is then implanted using the PSG as implant mask, thus only the area just below the gate received the ground plane implant. Poly silicon gate electrodes are formed through CMP and etch back after the gate oxidation. Our simulations have shown that the proposed device has substantial sub-threshold slope, short channel effects and DIBL reduction over no ground plane FDSOI MOSFETs. We fabricated the ground plane FDSOI MOSFETs down to 0.14μm-channel length and demonstrated significant improvements in device performance. For bulk silicon MOSFET, we proposed a MOSFET with symmetrical lateral gate work-function differences. The device gate is made out of two different work function materials: a higher work-function material is used for the center of the gate, and a lower work-function material s applied at the edges of the gate. As a result, the MOSFET experiences a Low-High-Low lateral V_th profile. The device shows both improved off-state leakage current control and enhanced short-channel effects immunity compared to a single-material gate MOSFET.