Clock distribution is increasingly becoming a very important issue in the design of computers, communication devices or advanced entertainment systems as these systems advance by adding higher performance and speedier microprocessors. These enhancements typically require incorporating higher frequency clock oscillators because the clock speed is directly proportional to the speed of the microprocessor processing the information. A higher processor speed also presents challenging problems for developing systems with low electromagnetic interference (EMI) in order to comply with the rules and regulations specified by the United States Federal Communication Commission (FCC). In this dissertation, a Gated Direct Sequence Spread Spectrum (GDSSS) clock distribution, where the original clock signal is being divided and spread over a wider frequency spectrum to reduce the radiated emissions, is proposed. Furthermore, this research demonstrates designs and simulations of innovative pseudo-random sequence generator, GDSSS transmitter and receiver circuits. Also, at the conclusion of the research, hardware including programmable logic devices and a system board, one GDSSS transmitter and three GDSSS receivers, is designed to validate this new and scalable clock distribution concept. This new concept lowers the radiated emissions without negatively affecting system timings or interfering with other noise sensitive circuits such as video, audio or graphics.
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