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The fabrication and characterization of MOSFETs with titanium dioxide and hafnium dioxide as gate dielectrics.

机译:以二氧化钛和二氧化ha作为栅极电介质的MOSFET的制造和表征。

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摘要

In this thesis, TiO2 and HfO2 films were studied as possible candidates. The films were deposited from their respective nitrato precursors using the MOCVD method. For TiO2 films, an interfacial layer was formed by thermal nitridation or plasma-aided nitridation of the silicon substrate surface prior to high permittivity film deposition.; The results obtained from TiO2 MOS capacitors and transistors indicated that the higher nitridation temperature results in higher concentration of nitrogen and more positive charge.; The best result in terms of EOT was obtained from TiO2 directly on silicon substrate samples. The positive charge in the interface is approximately on the high order of 1012 cm−2. The leakage current for TiO2 deposited directly on silicon with an EOT = 16 Å is about 4 orders of magnitude lower than that of 16 Å thermal SiO2 at −1.0 V bias. The maximum electron mobility is approximately 113 cm2/V·s, which is about one third of that for SiO 2/Si interface at the effective field investigated.; HfO2 films deposited at 300°C are monoclinic and oxygen rich. However, the excess oxygen seems to have no apparent effect on the electrical properties of films. The permittivity of HfO2 deposited at 300°C is 17. The interfacial layer is amorphous and believed to be an oxynitride.; The HfO2 film demonstrated excellent thermal stability. The HfO2 films can sustain at least a 1000°C 5 seconds anneal without degrading the film quality and causing additional interfacial layer growth.; n-MOSFETs and p-MOSFETs with HfO2 gate dielectrics were fabricated using a non-self aligned process. The minimum EOT achieved is 16 Å with polysilicon as the gate electrode. These transistors behave properly and demonstrated characteristics compatible to the oxynitride gate dielectrics. The n-channel subthreshold slope for HfO2 deposited at 300°C without annealing is approximately 76 mV/Dec, and high temperature annealing improved the subthreshold slope to 70 mV/Dec. P-channel devices, however, had a higher interface state density and larger inverse subthreshold slopes. Both the hole and electron mobility are approximately the same as conventional transistors with oxynitride as gate dielectrics.
机译:本文以TiO 2 和HfO 2 薄膜为研究对象。使用MOCVD方法从其各自的硝酸盐前体中沉积膜。对于TiO 2 薄膜,在高介电常数薄膜沉积之前,通过热氮化或等离子体辅助氮化对硅衬底表面形成界面层。 TiO 2 MOS电容器和晶体管的结果表明,较高的氮化温度导致较高的氮浓度和更多的正电荷。从EOT的最佳结果是直接从TiO 2 在硅衬底样品上获得的。界面中的正电荷大约为10 12 cm -2 的高阶。在-1.0 V偏压下,直接沉积在EOT = 16Å的硅上的TiO 2 的泄漏电流比16Å热SiO 2 的泄漏电流低约4个数量级。 。在研究的有效场上,最大电子迁移率约为113 cm 2 / V·s,约为SiO 2 / Si界面的电子迁移率的三分之一。在300°C沉积的HfO 2 膜是单斜晶且富含氧气。但是,过量的氧气似乎对薄膜的电性能没有明显影响。在300℃下沉积的HfO 2 的介电常数为17。界面层是非晶的,被认为是氮氧化物。 HfO 2 膜表现出优异的热稳定性。 HfO 2 膜可以承受至少1000°C 5秒的退火,而不会降低膜质量,不会引起其他界面层的生长。采用非自对准工艺制造了具有HfO 2 栅极电介质的n-MOSFET和p-MOSFET。使用多晶硅作为栅电极时,可实现的最小EOT为16。这些晶体管的性能正常,并具有与氮氧化物栅极电介质兼容的特性。在300℃下未经退火沉积的HfO 2 的n沟道亚阈值斜率约为76 mV / Dec,高温退火将亚阈值斜率提高至70 mV / Dec。但是,P沟道器件具有较高的界面态密度和较大的反亚阈值斜率。空穴迁移率和电子迁移率都与以氮氧化物为栅极电介质的常规晶体管大致相同。

著录项

  • 作者

    Ma, Tiezhong.;

  • 作者单位

    University of Minnesota.;

  • 授予单位 University of Minnesota.;
  • 学科 Engineering Electronics and Electrical.; Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 156 p.
  • 总页数 156
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;工程材料学;
  • 关键词

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