Reconfigurable computing is a new paradigm based on dynamically adapting the hardware to reconfigure the computation and communication structures on the chip. Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. Various reconfigurable devices have been developed by researchers and the industry. These devices promise a high degree of flexibility and superior performance. But, the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved.; This thesis addresses the fundamental challenges in achieving high performance using reconfigurable architectures. The diverse range of issues in mapping applications onto reconfigurable architectures are identified. A formal framework for mapping application tasks onto reconfigurable architectures is proposed in this thesis. The proposed framework includes a parameterized system level model, algorithmic mapping techniques and system level interpretive simulation environment.; A parameterized model of hybrid reconfigurable architectures, Hybrid System Architecture Model (HySAM), is developed to facilitate application mapping. Hybrid reconfigurable architectures include traditional processing units and memory on the same die as reconfigurable logic. The parameterized systems. Loop statements in traditional programs consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This thesis develops a formal methodology for to define and solve the problem of mapping loop statements onto reconfigurable architectures. The complexity of the problems and our proposed solutions is also addressed. Performance improvements are achieved on various architectures using our algorithmic techniques for mapping. In addition, existing design and simulation tools do not include the reconfiguration aspect in their methodology. A simulation methodology for reconfigurable architectures is proposed and validated by implementing a proof of concept tool. The Dynamically Reconfigurable systems Interpretive simulation and Visualization Environment (DRIVE) facilitates high level performance evaluation framework for design space exploration.
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