Test-based timing verification using functional techniques.

摘要

The problem of verifying the temporal correctness of VLSI circuits using test-based methodologies and the well established Path Delay Fault (PDF) model is examined. A circuit is considered delay-verifiable if its timing correctness can be demonstrated by applying appropriate input stimuli. This dissertation is focussed on the development of efficient Automatic Test Pattern Generators (ATPGs) to provide with test vectors that can detect timing failures in a circuit. The circuits under consideration are either combinational of fully-scanned with hold latches. The developed methods are based on appropriate formulation and manipulation of Boolean functions. Various functional frameworks are investigated.; Two different ATPG techniques are proposed to handle circuit descriptions gate (netlist) level. No structural information about the circuit is available the PDF model, are considered at this level. The test generation problem complexity increases at the netlist level, since the number of the faults under consideration (PDFs) can be exponential to the circuit size. We propose a non-fault enumerative ATPG methodology that provides with compact test sets. The proposed framework is especially attractive for dynamic test set compaction since the complete test sets for the targeted faults are implicitly maintained in the form of Boolean functions.; We also concentrate on the problem of fault propagation, which is a very important and time consuming tasks performed by an ATPG tool. A methodology that enables the generation of fault propagation functions by examining both circuit structure and functionality is presented. This enables fault propagation due to the occurrence of static hazards and, therefore, both functional (such as stuck-at) and delay faults can be propagated. Finally, the problem of implicit generation of the complete set of input pairs that may cause different types of hazards at a circuit line is studied. Besides facilitating delay testing and timing verification, this is a problem central to many other VLSI CAD problems such as circuit synthesis and re-synthesis and timing analysis.