Sigma-delta modulation in real-time three-dimensional sparse synthetic aperture ultrasound imaging systems.

摘要

This thesis examines the use of sigma-delta modulation in ultrasound systems, focusing specifically on sigma-delta-based sparse synthetic aperture beamforming for portable, real-time 3-D imaging. To date, work on real-time, 3-D imaging has focused largely on the use of 2-D transducer arrays with traditional beamformers based on Nyquist-rate A/D converters. Combining the techniques of sparse synthetic aperture beamforming with sigma-delta modulation and the latest IC fabrication technology allows the problem of 3-D imaging to be pursued with a smaller and more efficient linear phased array as the transducer.; An architecture based on sparse synthetic aperture beamforming, using second-order lowpass sigma-delta modulation for the A/D conversion, was developed. The beamformer is capable of producing over 1,000 2-D frames/s with secondary lobe levels at −54 dB and a beam width of 1.10, with the modulator providing λ/64 delay resolution. Furthermore, the effects of amplifier nonlinearity on the radiation pattern were studied in simulation, and show the beamformer to be relatively insensitive to nonlinearity.; The use of bandpass modulators in ultrasound systems was also studied. The beamformer model was extended to include a modification allowing for the use of band-pass sigma-delta modulation with input premodulation in this multi-beam system. Pre-modulation of the input in multi-beam systems is generally avoided because of the complexity of the phase-correction hardware that the beamformer requires. However, this work has shown that the special case of premodulation by f_s/4 with bandpass sigma-delta modulation allows a relatively simple phase-correction implementation.; Finally, a prototype of the analog front-end of the proposed system was designed and tested. An IC containing a 200-MHz double-sampled lowpass sigma-delta modulator, 2-stage preamplifier, and PLL clock multiplier was designed and fabricated in a 0.35-μm double-poly CMOS process. The sigma-delta modulator produces a peak 47 dB SNR at a sampling frequency of 7 MHz, and a peak SNR of 37 dB at a sampling frequency of 200 MHz, in both cases at an OSR of ∼30. The 2-stage preamplifier provides a maximum 60-dB of gain at over a 3-MHz bandwidth. The PLL multiplies an externally-provided reference clock by a factor of 8, and achieves a phase noise of ∼300 ps. The IC consumes 149 mW at a 200-MHz sampling frequency and occupies a die area of 0.40 mm2 (not including the pads).