A performance study of a low-latency, hybrid serial-parallel multiplier.

摘要

A performance study of a low latency most significant bit first (MSBF), hybrid multiplier architecture [1,2], (i.e., one input and the output operands are represented in radix-2 redundant number system and the other input operand is represented using two's compliment number system) is presented in this thesis. The design of the multiplier is based on a new 2-bit adder cell and another two new 2-bit adders. This multiplier differs from most multipliers in literature in that it is MSBF and hybrid. This multiplier requires fewer pipelining latches than in existing multiplier architectures and reduces the clock-speed for every cycle in the multiplication process. One 2N-digit product is produced every 2N+3 cycles. The serial-parallel multiplier would be simulated using VHDL (Very High Speed Integrated Circuits Hardware Description Language) followed by an implementation on a FLEX10K FPGA chip using Maxplus II software.