An implementation of a low power delta-sigma A/DC with a multi-bit quantizer on silicon-on-sapphire.

摘要

Scope and method of study. The technologically advancements of the chip fabrication and VLSI circuit design have propelled the concept of a system on chip. The unique architecture of the Delta-Sigma A/DC requiring both the modulator and the decimation filter on the same chip to reduce the power dissipation has directly benefited from these developments. The architectural advantage of the Delta-Sigma A/DC is its insensitivity to process variation allowing for resolution in excess of 20-bit by adjusting oversampling ratio, modulator order, and/or quantizer dimension. Moreover, recently available thin-film SOI/SOS processes provide excellent potential for circuit isolation and zero or negligible junction capacitors. The 2--3 times lower digital power consumption than the bulk processes and higher Q inductors of SOI/SOS attract applications in telecommunication and remote sensing areas, along with other applications that depend heavily on maintaining low power dissipation.; Finding and conclusion. The objective of this research was to develop a 1mW low power Delta-Sigma A/DC consisting of the 18-bit modulator at 2 Ksps and the decimation filter. This work has demonstrated: (1) that 2nd order A/DCs with a multi-bit quantizer is optimal in power/bit performance for high resolution A/DCs; (2) two-path decimation filters are more power efficient than Sine and Half-band filters. This work was verified by the implementation of a 2nd order modulator with a 4-bit quantizer and a 6 stage decimation filter. The single loop modulator was selected for its insensitivity to the process variation over MASH architecture. A parallel-to-serial shift-register (or serial) 1-bit D/AC was selected for its inherent linearity to implement quantizer feedback. The decimation filter is comprised of multiple two-path filters in cascade. It was demonstrated that the two-path filter decimation prior to the filtering doubles the power efficiency. In addition, the cascade approach required a lower filter order resulting in further reduction of the power dissipation. The designs were fabricated on Peregrine 0.5um SOS process. Powered by +/-1.5 V, the modulator was demonstrated to provide 13.5-bit at 128Ksps consuming 1.6mW. No resolution degradation was measured as a result of the decimation filter over DC to 23MHz. With the decimation filter power at 1.5 V, measured power dissipation was 1.5 uW at standby and 16.95uW at 128KHz.