A 6-bit 1.3 GSample/s A/D converter in 0.35-mum CMOS.

摘要

Digital receivers for high bit-rate communications are spurring on the conversion rate of A/D converters (ADCs). State-of-the-art disk drive read channels and high-speed Ethernet signals use partial response signaling, which requires 6-bit resolution at conversion rates of 1 GHz and beyond. Furthermore, continuous DVD playback and certain Ethernet uses permit no idle times when the linearity of the ADC may be self-calibrated by auto-zeroing.; The key features of this work are now summarized. A track-and-hold for this 6-bit ADC enables beyond Nyquist input up to 1.3 GHz conversion rate. Reset switches in the preamplifier and comparator arrays give fast overdrive recovery. The 2nd comparator is the fastest such CMOS circuit with rail-to-rail output. In this work, averaging networks are used in three places: first, to lower the impact of preamplifier static offset; second, to lower the latch dynamic offset; and third, to improve the preamplifier bandwidth by 3 times. These ideas have led to a compact CMOS analog-to-digital converter with unprecedented dynamic performance.; A 6-bit Nyquist A/D Converter that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-bit flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 GSample/s, and 5 effective bits for 650 MHz input at 1.3 GSample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB respectively. This ADC consumes about 500 mW from 3.3 V at 1 GSample/s. The chip occupies 0.8 mm2 active area fabricated in 0.35-mum CMOS.