SI-based stacked inductors for broadband circuit applications .

摘要

An ever increasing demand for high data rate broadband services into the foreseeable future means that CMOS solutions that transmit and receive data at high speeds with low error rates, low cost and low power will be needed. High-speed broadband circuits operating at bit rate of 10Gb/s - 40Gb/s or higher, usually require bandwidth enhancement. One of the most common techniques to implement bandwidth enhancement is inductive peaking however, it has the disadvantage of using large circuit area due to the large size of on chip transmission lines or kit inductors. This will lead to increased size and cost of an IC.;Finally, some amplifiers and stacked inductors are fabricated in the IBM 0.13mum CMOS process. Measurement results show that stacked inductors with a T-coil topology achieve up to a 73% bandwidth improvement while reducing the required chip area by 85% or more compared to using planar kit inductors from the manufacturer.;In this thesis, the performance of circuits that use stacked inductors for inductive peaking is compared with the performance that would have been achieved using of on chip transmission lines or kit inductors. Detail stacked spiral inductor design procedures are presented using ASITIC and HFSS modeling programs. The equivalent circuit of the stacked inductor is optimized in ADS using the modified 2-pi model for better performance matching. Different on-chip isolation techniques are also studied in order to reduce the unwanted coupling.