Fast waveform evaluation of logic stages by piecewise quadratic waveform matching.

摘要

While fast timing analysis methods based on model order reduction have been well established for linear circuits, the timing analysis for nonlinear circuits, which are dominant in digital circuits, is usually performed by a SPICE-like circuit simulator, which solves differential equations by numerical integration and Newton-Raphson method. This thesis presents a new technique that leads to the transient solution of charge/discharge paths with a complexity equivalent to only K DC operating point calculations, where K is the number of transistors along the path. This is accomplished by approximating each nodal voltage as a piecewise quadratic waveform, the characteristics of which can be determined by matching the charge/discharge currents. Experiments on a wide range of circuits show that an average speed-up above 30 over SPICE transient simulation can be achieved, while maintaining an average accuracy of 98%.