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Integrated Solutions for Timing Jitter Measurement.

机译:时序抖动测量的集成解决方案。

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摘要

In this thesis we present two integrated solutions suitable for measuring the timing jitter of digital signals in SoCs and data acquisition systems (mainly sampling ADCs). The presented methods are also suitable for time measurement in a variety of timing-based metrological applications.;The second method consist of an ADC-based jitter measurement technique in which the jittery signal assumes the role of sampling clock. The novelty in this technique is that it supports arbitrary analog inputs to the ADC as measurement vehicle. The proposed measurement system comprises, in addition to the sampling ADC, an independent back-end digital system to extract jitter timing information. A very important feature of such a digital system is that the jitter-induced magnitude error in each output sample of the ADC is first measured before extracting its associated timing information. Jitter characteristics of the sampling clock are extracted with high accuracy. Indeed, as demonstrated in this thesis, even for an input signal to the ADC with a bandwidth as small as 4.61 MHz, the jitter distribution of a 12.5 MHz sampling clock is extracted with an accuracy of about 3.25 ps.;The first method is based on the amplification of the time difference to be measured using a time amplifier (TAMP). The result of the amplification is subsequently digitized using a low resolution time-to-digital converter (TDC). The amplifier is based on the principle of virtual charge sharing that allows for continuous, monotonic and symmetric time transfer characteristics. Given its analog nature, the time amplifier has linearity issues in addition to being prone to temperature and process variations and uncertainties. To address these problems, a measurement and calibration method that consists of a dual TAMP arrangement is used to deduce the measured timing quantities without a priori knowledge of the gain of the amplifiers. Also, an empirical and more direct calibration technique suitable for a single-amplifier-based measurement system is presented. In this thesis we implement an amplifier with a measured gain of 228 s/s feeding a TDC of 78 ps of resolution resulting in a timing measurement system of 342.1 fs of nominal resolution.
机译:在本文中,我们提出了两种适用于测量SoC和数据采集系统(主要是采样ADC)中数字信号的时序抖动的集成解决方案。所提出的方法也适用于各种基于时序的计量应用中的时间测量。第二种方法包括基于ADC的抖动测量技术,其中抖动信号承担采样时钟的作用。该技术的新颖之处在于,它支持将任意模拟输入作为测量工具传输到ADC。所提出的测量系统除采样ADC外,还包括一个独立的后端数字系统,用于提取抖动时序信息。这种数字系统的一个非常重要的特征是,在提取ADC的相关时序信息之前,首先测量ADC的每个输出采样中的抖动引起的幅度误差。高精度提取采样时钟的抖动特性。实际上,正如本论文所论证的那样,即使对于带宽小至4.61 MHz的ADC输入信号,也能以大约3.25 ps的精度提取12.5 MHz采样时钟的抖动分布。使用时间放大器(TAMP)放大要测量的时差。随后,使用低分辨率时间数字转换器(TDC)将放大结果数字化。该放大器基于虚拟电荷共享原理,该原理允许连续,单调和对称的时间传递特性。鉴于其模拟性质,时间放大器除了容易出现温度和工艺变化以及不确定性外,还存在线性问题。为了解决这些问题,在没有先验知识放大器增益的情况下,使用由双重TAMP装置组成的测量和校准方法来推导测量的时序量。此外,提出了一种适用于基于单放大器的测量系统的经验性和更直接的校准技术。在本文中,我们实现了一种放大器,其测量增益为228 s / s,馈送了分辨率为78 ps的TDC,从而形成了标称分辨率为342.1 fs的时序测量系统。

著录项

  • 作者

    Oulmane, Mourad.;

  • 作者单位

    McGill University (Canada).;

  • 授予单位 McGill University (Canada).;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 139 p.
  • 总页数 139
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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