Cost-effective test methodologies for mixed-signal components in system-on-chip.

摘要

As consumer demand increases for cheaper, smaller and more portable electronic devices, single-chip systems become increasingly necessary. Providing a single-chip solution requires that different types of components be integrated into a single chip, generally referred to as the mixed-signal System-on-Chip (SoC). Such integration increases the challenge of designing and the cost of testing SoCs. Testing these high-technology SoCs requires several types of expensive, high-performance Automatic Test Equipment (ATE) to ensure the quality and the reliability of these integrated systems. In addition to escalating the testing cost, multiple probes of ATEs pressing down upon the SoCs' wafers can cause wear that reduces the microchip reliability.; This dissertation philosophy centers upon formulating solutions to enhance the SoCs self-testing capability or to enable a single ATE test to suffice for SoCs quality control. The work can be categorized into three major areas. The first area provides a self-test solution for general Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) commonly found in the mixed-signal SoCs. Providing self-test solutions to these converters will not only reduce the test cost, but also increase the SoC reliability from alleviating the stress of repeated ATE testing on the SoCs. After the converters are tested, they can be used for testing other analog/mixed-signal components in the SoCs.; The second area concerns a new testing technique for the delta-sigma-based ADCs. This technique utilizes a digital stimulus to test delta-sigma-based ADCs, which are usually tested with an analog stimulus. This new technique removes the deadlock commonly found in self-testing of SoC analog components, because the signal generator and signal digitizer are inter-dependent during self-testing. Hence, SoCs with a delta-sigma ADC would benefit from this technique.; The third area concerns a new technique to analyze signals' jitter characteristics. Most existing jitter analyses are histogram-based, concealing jitter sequential information and distorting the true random jitter of a signal. Histogram analysis therefore might misevaluate performance of systems that adapt to some drift in the signal frequency. Our counter-based technique could extract the spectral information of the jitter. This extracted spectral information could provide more accurate means of evaluating the systems' performance.