Design, characterization and automation of an ultra-high-temperature standard cell library for harsh environments.

摘要

The purpose of this study is to design a cell library that can be used to construct ultra-high temperature CMOS application specific integrated circuits (ASIC). The design methodology focuses on all aspects circuit design for ultra-high temperature operation such as minimizing off state leakage and maximizing noise margin. The cell library is designed and simulated in Cadence design suite. Each cell in the library is characterized using OCEAN script for delay using a linear delay model, which allows easier characterization of the cells with a limited number of simulations, while still achieving reasonable accuracy. The library is comprised of over 90 cells including both logic and I/O pads. A calibration model is developed which ensures accurate hardware delay calibration of the library while reducing the number of cell measurements by a factor of six.