Low-power multi-threshold CMOS circuits optimization and CAD tool design.

摘要

As technology scales into the Deep Sub-Micron regime (DSM), standby subthreshold leakage power increases exponentially with the reduction of the threshold voltage. Therefore, effective leakage minimization techniques are a necessity. In addition, for a true low-power solution, it needs to be integrated into the principal design environment. In this thesis, two genetic algorithms are implemented to efficiently solve the Bin-Packing (BP) and the Set-Partitioning (SP) problems in the gate-clustering MTCMOS technique. Also, two design techniques are proposed to effectively solve the sleep transistor sizing problem in MTCMOS circuits. The introduced First-Fit (FF) and Set-Covering (SC) approaches achieve a lower leakage at an order of magnitude reduction in the CPU time, compared to those of other techniques in the literature. In addition, an automatic MTCMOS design environment is devised and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.