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Matrix transform imager architecture for on-chip low-power image processing.

机译:用于片上低功耗图像处理的矩阵变换成像器体系结构。

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摘要

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones.; In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating-gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent---comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image.; The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.
机译:片上摄像头系统已尝试包括精心选择的信号处理单元,以实现更好的功能,性能并扩大其可用于的应用范围。由于CMOS有源像素传感器(APS)和神经形态焦平面成像仪的发展,图像处理传感器已成为可能。这些系统的一些优势是紧凑的尺寸,高速和并行性,低功耗以及密集的系统集成。可以设想将这些芯片用于诸如个人数字助理(PDA)或手机之类的手持设备上的便携式廉价摄像机。在视网膜的神经形态建模中,在保持典型APS成像器设计密度的同时,在焦平面具有处理能力将是非常好的。不幸的是,这两个目标几乎是不相容的。我们介绍我们的MAtrix变换成像仪体系结构(MATIA),该体系结构使用模拟浮动门设备使具有高像素密度的计算成像仪成为可能。核心成像器在像素平面上执行计算,但仍然具有46%的填充率,与APS成像器的高填充率相比。通过可对整个图像或图像中的块进行操作的可编程矩阵运算,对图像进行连续处理。产生的数据流体系结构可以直接执行各种块矩阵图像转换。由于成像器在亚阈值区域内运行,因此功耗很低,因此对于使用这些计算的任何系统,此体系结构都可用作低功耗前端。可以使用此架构来实现使用块矩阵变换的各种压缩算法(例如JPEG)。由于MATIA可以用于梯度计算,因此可以使用此体系结构实现廉价的图像跟踪设备。该体系结构的其他应用范围可以从独立的通用变换成像器系统到可以计算立体深度的系统。

著录项

  • 作者

    Bandyopadhyay, Abhishek.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 180 p.
  • 总页数 180
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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