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Strain effects in low-dimensional silicon MOS and AlGaN/GaN HEMT devices.

机译:低维硅MOS和AlGaN / GaN HEMT器件中的应变效应。

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摘要

Strained silicon technology is a well established method to enhance sub-100nm MOSFET performance. With the scalability of process-induced strain, strained silicon channels have been used in every advanced CMOS technology since the 90nm node. At the 22nm node, due to the detrimental short channel effects, non-planar silicon CMOS has emerged as a viable solution to sustain transistor scaling without compromising the device performance. Therefore, it is necessary to conduct a physics based investigation of the effects of mechanical strain in silicon MOS device performance enhancement, as the transverse and longitudinal device dimensions scale down for future technology nodes.;While silicon is widely used as the material basis for logic transistors, AlGaN/GaN HEMTs promise a superior device platform over silicon based power MOSFETs for high-frequency and high-power applications. In contrast to the mature Si crystal growth technology, the abundance of defects in the GaN material system creates obstacles for the realization of a reliable AlGaN/GaN HEMT device technology. Due to the high levels of internal mechanical strain present in AlGaN/GaN HEMTs, it is of utmost importance to understand the impact of mechanical stress on AlGaN/GaN trap generation.;First, we have investigated the underlying physics of the comparable electron mobility observed in (100) and (110) sidewall silicon double-gate FinFETs, which is different from the observed planar (100) and (110) electron mobility. By conducting a systematic experimental study, it is shown that the undoped body, metal gate induced stress, and volume-inversion effects do not explain the comparable electron mobility. Using a self-consistent double-gate FinFET simulator, we have showed that for (110) FinFETs, an increased population of electrons is obtained for the Delta2 valley due to the heavy nonparabolic confinement mass, leading to a comparable average electron transport effective mass for both orientations.;The width dependent strain response of tri-gate p-type FinFETs are experimentally extracted using a 4-point bending jig. It is found that the low-field piezoresistance coefficient of p-type FinFETs can be modeled by using a weighted conductance average of the top and sidewall bulk piezoresistance coefficients.;Next, the strain enhancement of p-type ballistic silicon nanowire MOSFETs is studied using sp3d 5s* basis nearest-neighbor tight-binding simulations coupled with a semiclassical top-of-the-barrier transport model. Size and orientation dependent strain enhancement of ballistic hole transport is explained by the strain-induced modification of the 1D nanowire valence band density-of-states. Further insights are provided for future p-type high-performance silicon nanowire logic devices.;A physics based investigation is conducted to understand the strain effects on surface roughness limited electron mobility in silicon inversion layers. Based on the evidence from electrical and material characterization, a strain-induced surface morphology change is hypothesized. To model the observed electrical characteristics, we have employed a self-consistent MOSFET mobility simulator coupled with an ad hoc strain-induced roughness modification. The strain induced surface morphology change is found to be consistent among electrical and materials characterization, as well as transport simulations.;In order to bridge the gap between the drift-diffusion based models for long-channel devices and the quasi-ballistic models for nanoscale channels, a unified carrier transport model is developed using an updated one-flux theory. Including the high-field and carrier confinement effects, a surface-potential based analytical transmission expression is obtained for the entire MOSFET operation range. With the new channel transmission equation and average carrier drift velocity, a new expression for channel ballisticity is defined. Impact of mechanical strain on carrier transport for both nMOSFETs and pMOSFETs in both linear and saturation regimes is explained using the new channel transmission definitions.;To understand the impact of mechanical strain on AlGaN/GaN HEMT trap generation, we have devised an experimental method to obtain the photon flux-normalized relative areal trap density distribution using photoionization spectroscopy technique. The details of the trap extraction method and the experimental setup are given. Using this setup, the trap characteristics are extracted for both ungated transmission line module (TLM) and gated HEMT devices from both Si and SiC substrates. The changes in the device trap characteristics are emphasized before and after electrical stressing. It is found through the step-voltage stressing of the AlGaN/GaN HEMT gate stack that the device degradation is due to the near bandgap trap generation, which are shown to be related to the structural defects in GaN.
机译:应变硅技术是提高100nm以下MOSFET性能的成熟方法。由于工艺引起的应变具有可扩展性,自90纳米节点以来,应变硅通道已用于每一种先进的CMOS技术中。在22nm节点上,由于有害的短沟道效应,非平面硅CMOS已成为一种可行的解决方案,可在不影响器件性能的情况下维持晶体管的缩放。因此,有必要对物理应变对硅MOS器件性能增强的影响进行基于物理的研究,因为横向和纵向器件尺寸会随着未来技术节点的发展而缩小。;尽管硅被广泛用作逻辑的材料基础晶体管,AlGaN / GaN HEMT有望为高频和大功率应用提供优于硅基功率MOSFET的出色器件平台。与成熟的Si晶体生长技术相比,GaN材料系统中大量的缺陷为实现可靠的AlGaN / GaN HEMT器件技术带来了障碍。由于AlGaN / GaN HEMT中存在很高的内部机械应变,因此了解机械应力对AlGaN / GaN陷阱生成的影响至关重要。首先,我们研究了可观察到的可比电子迁移率的基本物理原理在(100)和(110)侧壁硅双栅FinFET中,这与观察到的平面(100)和(110)电子迁移率不同。通过进行系统的实验研究,表明未掺杂的体,金属栅极引起的应力和体积反转效应不能解释可比的电子迁移率。使用自洽双栅极FinFET仿真器,我们已经表明,对于(110)FinFET,由于重的非抛物线约束质量,对于Delta2谷,获得了更多的电子,从而获得了可比的平均电子传输有效质量。使用四点弯曲夹具实验性地提取了三栅极p型FinFET的宽度相关应变响应。研究发现,可以利用顶部和侧壁体压阻系数的加权平均电导率对p型FinFET的低场压阻系数进行建模。 sp3d 5s *基础最近邻紧密绑定模拟,加上半经典障碍物传输模型。弹道空穴传输的尺寸和取向依赖性应变增强通过一维纳米线价带态密度的应变诱导修饰来解释。为未来的p型高性能硅纳米线逻辑器件提供了进一步的见解。进行了基于物理学的研究,以了解应变对硅反型层中表面粗糙度限制的电子迁移率的影响。基于电学和材料表征的证据,假设了应变引起的表面形态变化。为了对观察到的电特性进行建模,我们采用了自相容的MOSFET迁移率仿真器,并结合了应变自发引起的粗糙度修正。发现应变引起的表面形态变化在电学和材料表征以及传输模拟之间是一致的;为了弥合基于漂移扩散的长通道器件模型与准弹道模型之间的差距通道,使用更新的单通量理论开发统一的运输工具运输模型。包括高场和载流子限制效应,在整个MOSFET工作范围内均获得了基于表面电势的解析传输表达式。利用新的信道传输方程和平均载波漂移速度,定义了信道弹道的新表达式。使用新的通道传输定义解释了线性和饱和状态下机械应变对nMOSFET和pMOSFET载流子输运的影响。为了了解机械应变对AlGaN / GaN HEMT陷阱产生的影响,我们设计了一种实验方法来使用光电离光谱技术获得光子通量归一化的相对面积陷阱密度分布。给出了捕集阱提取方法和实验装置的详细信息。使用此设置,可以从Si和SiC基板中提取非门控传输线模块(TLM)和门控HEMT器件的陷阱特性。在施加电应力之前和之后,都强调了器件陷阱特性的变化。通过AlGaN / GaN HEMT栅极堆叠的阶跃电压应力发现,器件性能下降是由于产生了近带隙陷阱,这与GaN中的结构缺陷有关。

著录项

  • 作者

    Baykan, Mehmet Onur.;

  • 作者单位

    University of Florida.;

  • 授予单位 University of Florida.;
  • 学科 Engineering Electronics and Electrical.;Physics Condensed Matter.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 193 p.
  • 总页数 193
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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