Secure and Architectural Design Exploration for Testing of 2D/3D SoCs.

摘要

As the complexity of system-on-chips is increasing, new problems for testing and test architecture design are emerging. In this work, a few emerging challenges in test architecture design of modern system-on-chips are discussed. All these proposed works aim at reducing testing time and tester data volume overhead.;For an IP core containing multiple clock domains, a power constrained core test wrapper is proposed. This wrapper performs clock control during pattern shift and response capture. There are multiple choices for shift frequency for each clock domain. A scan chain segmentation based approach is used to reduce power dissipation during pattern shift. The approach is named serial-parallel shift. When some domains are shifting, others are gated off. Shift frequency of each clock domain is determined by a heuristic. Simulations show that the proposed approach considerably reduces pattern shifting time compared to previous wrapper designs.;In order to improve scan security of crypto chips while not compromising test coverage, two test control gating based secure scan architectures are proposed. In both schemes, each scan chain is divided into two sets. In both methods, scan chains are partitioned into two sets. The set closest to the input side is controlled by external TC. The second set is controlled by the internal gated value of TC. The proposed scheme is robust against side-channel attacks. This method also has much less testing time overhead compared to previous approaches.;The final yield of a stacked chip depends on the quality of die used. However, die testing is constrained by very limited test pad count. To improve testing time and avoid structural damage to bare die, contactless probing has been suggested as an alternative to touchdown probing. An inductive coupling based test architecture that can simultaneously provide test control signals to on-die TSV BIST and test stimulus to IP cores is also presented. A broadcast based scheme is used for reducing bandwidth wastage while testing the TSVs. A test architecture design algorithm for improving TSV and core test parallelism is also proposed. This algorithm achieves die testing time close to theoretical lower bound.