VHDL simulation for reduction of state space representation of linear sequential machines.

摘要

FPGA implementation is becoming popular because of its role in VLSI. In this thesis FPGA implementation of state space models is taken up. State space models have generated interest in control theory for the last four decades. State models have been used in a variety of applications. Equivalent state models are those models in which new A, B, C, D are of the same order, but their implementation may result in different circuits. Out of various circuits, the best model can be chosen which may result in a minimum number of components. In this thesis, an algorithm for the reduction of linear sequential circuits especially suitable for FPGA implementation is proposed. The proposed algorithm is implemented on a FPGA chip. The procedure requires FGPA implementation of several matrix operations, which are otherwise not commonly found in literature. In this present work, as we are dealing with modulo-2 operations only, the matrix operations are translated in the form of 'AND', 'XOR', if-then and if-then-else operations which are then implemented on FPGA. The simulation results are included. FPGA implementation flow-charts and VHDL codes are also included. It is hoped that this thesis will lead to the FPGA implementation of a variety of different circuits not implemented so far. Such implementations will results in more fruitful results on chip implementation of state space models. Further, this methodology will result in wider implementation of state space models on chips, opening new possibilities in low cost control engineering.